📄 we.map.rpt.htm
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<TD ALIGN="LEFT">we.bdf</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">User Block Diagram/Schematic File </TD>
<TD ALIGN="LEFT">D:/PLD/FPGAlicheng/music/we.bdf</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">TONETABA.vhd</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">User VHDL File </TD>
<TD ALIGN="LEFT">D:/PLD/FPGAlicheng/music/TONETABA.vhd</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">NoteTabs.vhd</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">User VHDL File </TD>
<TD ALIGN="LEFT">D:/PLD/FPGAlicheng/music/NoteTabs.vhd</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">lpm_rom0.tdf</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">User AHDL File </TD>
<TD ALIGN="LEFT">D:/PLD/FPGAlicheng/music/lpm_rom0.tdf</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">altsyncram.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/altera/quartus60/libraries/megafunctions/altsyncram.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">altsyncram.tdf</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Megafunction </TD>
<TD ALIGN="LEFT">c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">stratix_ram_block.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/altera/quartus60/libraries/megafunctions/stratix_ram_block.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">lpm_mux.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/altera/quartus60/libraries/megafunctions/lpm_mux.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">lpm_decode.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/altera/quartus60/libraries/megafunctions/lpm_decode.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">aglobal60.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/altera/quartus60/libraries/megafunctions/aglobal60.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">a_rdenreg.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/altera/quartus60/libraries/megafunctions/a_rdenreg.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">altrom.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/altera/quartus60/libraries/megafunctions/altrom.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">altram.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/altera/quartus60/libraries/megafunctions/altram.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">altdpram.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/altera/quartus60/libraries/megafunctions/altdpram.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">altqpram.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/altera/quartus60/libraries/megafunctions/altqpram.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">db/altsyncram_f431.tdf</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Auto-Generated Megafunction </TD>
<TD ALIGN="LEFT">D:/PLD/FPGAlicheng/music/db/altsyncram_f431.tdf</TD>
</TR>
</TABLE>
<P><A NAME="5"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Analysis & Synthesis Resource Usage Summary</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Resource</TH>
<TH>Usage</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total logic elements</TD>
<TD ALIGN="LEFT">19</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- Combinational with no register</TD>
<TD ALIGN="LEFT">11</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- Register only</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- Combinational with a register</TD>
<TD ALIGN="LEFT">8</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Logic element usage by number of LUT inputs</TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- 4 input functions</TD>
<TD ALIGN="LEFT">3</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- 3 input functions</TD>
<TD ALIGN="LEFT">7</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- 2 input functions</TD>
<TD ALIGN="LEFT">8</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- 1 input functions</TD>
<TD ALIGN="LEFT">1</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- 0 input functions</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- Combinational cells for routing</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Logic elements by mode</TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- normal mode</TD>
<TD ALIGN="LEFT">13</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- arithmetic mode</TD>
<TD ALIGN="LEFT">6</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- qfbk mode</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- register cascade mode</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- synchronous clear/load mode</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- asynchronous clear/load mode</TD>
<TD ALIGN="LEFT">8</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total registers</TD>
<TD ALIGN="LEFT">8</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total logic cells in carry chains</TD>
<TD ALIGN="LEFT">7</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">I/O pins</TD>
<TD ALIGN="LEFT">8</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total memory bits</TD>
<TD ALIGN="LEFT">1024</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Maximum fan-out node</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Maximum fan-out</TD>
<TD ALIGN="LEFT">12</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total fan-out</TD>
<TD ALIGN="LEFT">106</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Average fan-out</TD>
<TD ALIGN="LEFT">3.42</TD>
</TR>
</TABLE>
<P><A NAME="6"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Analysis & Synthesis Resource Utilization by Entity</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Compilation Hierarchy Node</TH>
<TH>Logic Cells</TH>
<TH>LC Registers</TH>
<TH>Memory Bits</TH>
<TH>M512s</TH>
<TH>M4Ks</TH>
<TH>M-RAMs</TH>
<TH>DSP Elements</TH>
<TH>DSP 9x9</TH>
<TH>DSP 18x18</TH>
<TH>DSP 36x36</TH>
<TH>Pins</TH>
<TH>Virtual Pins</TH>
<TH>LUT-Only LCs</TH>
<TH>Register-Only LCs</TH>
<TH>LUT/Register LCs</TH>
<TH>Carry Chain LCs</TH>
<TH>Packed LCs</TH>
<TH>Full Hierarchy Name</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">|we</TD>
<TD ALIGN="LEFT">19 (0)</TD>
<TD ALIGN="LEFT">8</TD>
<TD ALIGN="LEFT">1024</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">8</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">11 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">8 (0)</TD>
<TD ALIGN="LEFT">7 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">|we</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> |NoteTabs:inst3|</TD>
<TD ALIGN="LEFT">11 (11)</TD>
<TD ALIGN="LEFT">8</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">3 (3)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">8 (8)</TD>
<TD ALIGN="LEFT">7 (7)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">|we|NoteTabs:inst3</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> |TONETABA:inst2|</TD>
<TD ALIGN="LEFT">8 (8)</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">8 (8)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">|we|TONETABA:inst2</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> |lpm_rom0:inst|</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">1024</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">|we|lpm_rom0:inst</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> |altsyncram:altsyncram_component|</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">1024</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">|we|lpm_rom0:inst|altsyncram:altsyncram_component</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> |altsyncram_f431:auto_generated|</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">1024</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">|we|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated</TD>
</TR>
</TABLE>
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.<br>
<P><A NAME="7"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Analysis & Synthesis RAM Summary</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Name</TH>
<TH>Type</TH>
<TH>Mode</TH>
<TH>Port A Depth</TH>
<TH>Port A Width</TH>
<TH>Port B Depth</TH>
<TH>Port B Width</TH>
<TH>Size</TH>
<TH>MIF</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ALTSYNCRAM</TD>
<TD ALIGN="LEFT">AUTO</TD>
<TD ALIGN="LEFT">ROM</TD>
<TD ALIGN="LEFT">256</TD>
<TD ALIGN="LEFT">4</TD>
<TD ALIGN="LEFT">--</TD>
<TD ALIGN="LEFT">--</TD>
<TD ALIGN="LEFT">1024</TD>
<TD ALIGN="LEFT">YINYUE.mif</TD>
</TR>
</TABLE>
<P><A NAME="8"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>User-Specified and Inferred Latches</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Latch Name</TH>
<TH>Latch Enable Signal</TH>
<TH>Free of Timing Hazards</TH>
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