we.map.rpt.htm

来自「出血FPGA,用VHDL做的音乐盒」· HTM 代码 · 共 1,239 行 · 第 1/3 页

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</TR>
<TR valign="middle">
<TD ALIGN="LEFT">TONETABA:inst2|HIGH</TD>
<TD ALIGN="LEFT">TONETABA:inst2|Mux4</TD>
<TD ALIGN="LEFT">yes</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">TONETABA:inst2|CODE[2]</TD>
<TD ALIGN="LEFT">TONETABA:inst2|Mux4</TD>
<TD ALIGN="LEFT">yes</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">TONETABA:inst2|CODE[1]</TD>
<TD ALIGN="LEFT">TONETABA:inst2|Mux4</TD>
<TD ALIGN="LEFT">yes</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">TONETABA:inst2|CODE[0]</TD>
<TD ALIGN="LEFT">TONETABA:inst2|Mux4</TD>
<TD ALIGN="LEFT">yes</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Number of user-specified and inferred latches = 4 </TD>
<TD ALIGN="LEFT">&nbsp;</TD>
<TD ALIGN="LEFT">&nbsp;</TD>
</TR>
</TABLE>
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.<br>
<P><A NAME="9"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>General Register Statistics</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Statistic</TH>
<TH>Value</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total registers</TD>
<TD ALIGN="LEFT">8</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Number of registers using Synchronous Clear</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Number of registers using Synchronous Load</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Number of registers using Asynchronous Clear</TD>
<TD ALIGN="LEFT">8</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Number of registers using Asynchronous Load</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Number of registers using Clock Enable</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Number of registers using Preset</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
</TABLE>
<P><A NAME="10"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Source assignments for lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Assignment</TH>
<TH>Value</TH>
<TH>From</TH>
<TH>To</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">OPTIMIZE_POWER_DURING_SYNTHESIS</TD>
<TD ALIGN="LEFT">NORMAL_COMPILATION</TD>
<TD ALIGN="LEFT">-</TD>
<TD ALIGN="LEFT">-</TD>
</TR>
</TABLE>
<P><A NAME="11"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Parameter Settings for User Entity Instance: lpm_rom0:inst|altsyncram:altsyncram_component</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Parameter Name</TH>
<TH>Value</TH>
<TH>Type</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">BYTE_SIZE_BLOCK</TD>
<TD ALIGN="LEFT">8</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">AUTO_CARRY_CHAINS</TD>
<TD ALIGN="LEFT">ON</TD>
<TD ALIGN="LEFT">AUTO_CARRY</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">IGNORE_CARRY_BUFFERS</TD>
<TD ALIGN="LEFT">OFF</TD>
<TD ALIGN="LEFT">IGNORE_CARRY</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">AUTO_CASCADE_CHAINS</TD>
<TD ALIGN="LEFT">ON</TD>
<TD ALIGN="LEFT">AUTO_CASCADE</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">IGNORE_CASCADE_BUFFERS</TD>
<TD ALIGN="LEFT">OFF</TD>
<TD ALIGN="LEFT">IGNORE_CASCADE</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">OPERATION_MODE</TD>
<TD ALIGN="LEFT">ROM</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">WIDTH_A</TD>
<TD ALIGN="LEFT">4</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">WIDTHAD_A</TD>
<TD ALIGN="LEFT">8</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">NUMWORDS_A</TD>
<TD ALIGN="LEFT">256</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">OUTDATA_REG_A</TD>
<TD ALIGN="LEFT">CLOCK0</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">ADDRESS_ACLR_A</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">OUTDATA_ACLR_A</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">WRCONTROL_ACLR_A</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">INDATA_ACLR_A</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">BYTEENA_ACLR_A</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">WIDTH_B</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">WIDTHAD_B</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">NUMWORDS_B</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">INDATA_REG_B</TD>
<TD ALIGN="LEFT">CLOCK1</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">WRCONTROL_WRADDRESS_REG_B</TD>
<TD ALIGN="LEFT">CLOCK1</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">RDCONTROL_REG_B</TD>
<TD ALIGN="LEFT">CLOCK1</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">ADDRESS_REG_B</TD>
<TD ALIGN="LEFT">CLOCK1</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">OUTDATA_REG_B</TD>
<TD ALIGN="LEFT">UNREGISTERED</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">BYTEENA_REG_B</TD>
<TD ALIGN="LEFT">CLOCK1</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">INDATA_ACLR_B</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">WRCONTROL_ACLR_B</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">ADDRESS_ACLR_B</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">OUTDATA_ACLR_B</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">RDCONTROL_ACLR_B</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">BYTEENA_ACLR_B</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">WIDTH_BYTEENA_A</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">WIDTH_BYTEENA_B</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">RAM_BLOCK_TYPE</TD>
<TD ALIGN="LEFT">AUTO</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">BYTE_SIZE</TD>
<TD ALIGN="LEFT">8</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">READ_DURING_WRITE_MODE_MIXED_PORTS</TD>
<TD ALIGN="LEFT">DONT_CARE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">INIT_FILE</TD>
<TD ALIGN="LEFT">YINYUE.mif</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">INIT_FILE_LAYOUT</TD>
<TD ALIGN="LEFT">PORT_A</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">MAXIMUM_DEPTH</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">CLOCK_ENABLE_INPUT_A</TD>
<TD ALIGN="LEFT">NORMAL</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">CLOCK_ENABLE_INPUT_B</TD>
<TD ALIGN="LEFT">NORMAL</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">CLOCK_ENABLE_OUTPUT_A</TD>
<TD ALIGN="LEFT">NORMAL</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">CLOCK_ENABLE_OUTPUT_B</TD>
<TD ALIGN="LEFT">NORMAL</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">DEVICE_FAMILY</TD>
<TD ALIGN="LEFT">Stratix</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">CBXI_PARAMETER</TD>
<TD ALIGN="LEFT">altsyncram_f431</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
</TABLE>
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".<br>
<P><A NAME="12"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Analysis & Synthesis Equations</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<a href="file:///D:/PLD/FPGAlicheng/music/we.map.eqn.htm">Analysis & Synthesis Equations</a><BR>
<P><A NAME="13"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Analysis & Synthesis Messages</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<PRE>
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Sep 23 20:21:50 2008
Info: Command: quartus_map --lower_priority --read_settings_files=on --write_settings_files=off we -c we
Info: Found 2 design units, including 1 entities, in source file SHUKONGDIV.vhd
    Info: Found design unit 1: SHUKONG_DIV-MA
    Info: Found entity 1: SHUKONG_DIV
Info: Found 2 design units, including 1 entities, in source file SPEAKER.vhd
    Info: Found design unit 1: SPEAKER-MA
    Info: Found entity 1: SPEAKER
Info: Found 1 design units, including 1 entities, in source file we.bdf
    Info: Found entity 1: we
Info: Found 2 design units, including 1 entities, in source file TONETABA.vhd
    Info: Found design unit 1: TONETABA-MA
    Info: Found entity 1: TONETABA
Info: Found 2 design units, including 1 entities, in source file NoteTabs.vhd
    Info: Found design unit 1: NoteTabs-one
    Info: Found entity 1: NoteTabs
Warning: Can't analyze file -- file D:/PLD/FPGAlicheng/music/lpm_rom1.tdf is missing
Info: Found 1 design units, including 1 entities, in source file lpm_rom0.tdf
    Info: Found entity 1: lpm_rom0
Info: Elaborating entity "we" for the top level hierarchy
Info: Elaborating entity "TONETABA" for hierarchy "TONETABA:inst2"
Warning (10631): VHDL Process Statement warning at TONETABA.vhd(12): inferring latch(es) for signal or variable "TONE", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at TONETABA.vhd(12): inferring latch(es) for signal or variable "CODE", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at TONETABA.vhd(12): inferring latch(es) for signal or variable "HIGH", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "HIGH"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "CODE[0]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "CODE[1]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "CODE[2]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "CODE[3]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[0]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[1]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[2]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[3]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[4]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[5]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[6]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[7]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[8]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[9]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[10]"
Info: Elaborating entity "lpm_rom0" for hierarchy "lpm_rom0:inst"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "lpm_rom0:inst|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "lpm_rom0:inst|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_f431.tdf
    Info: Found entity 1: altsyncram_f431
Info: Elaborating entity "altsyncram_f431" for hierarchy "lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated"
Info: Elaborating entity "NoteTabs" for hierarchy "NoteTabs:inst3"
Info: Elaborating entity "SPEAKER" for hierarchy "SPEAKER:inst1"
Warning (10036): Verilog HDL or VHDL warning at SPEAKER.vhd(10): object "FULLSPKS" assigned a value but never read
Warning (10034): Output port "SPKS" at SPEAKER.vhd(7) has no driver
Warning: Entity "SPEAKER" contains only dangling pins
Warning: Latch TONETABA:inst2|HIGH has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3]
Warning: Latch TONETABA:inst2|CODE[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[2]
Warning: Latch TONETABA:inst2|CODE[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[1]
Warning: Latch TONETABA:inst2|CODE[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[0]
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "SPKS" stuck at GND
    Warning: Pin "CODE[3]" stuck at GND
Warning: Design contains 1 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "CLK12M"
Info: Implemented 31 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 6 output pins
    Info: Implemented 19 logic cells
    Info: Implemented 4 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 20 warnings
    Info: Processing ended: Tue Sep 23 20:21:51 2008
    Info: Elapsed time: 00:00:02
</PRE>
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