📄 we.cmp.rpt.htm
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<TH>M512s</TH>
<TH>M4Ks</TH>
<TH>M-RAMs</TH>
<TH>DSP Elements</TH>
<TH>DSP 9x9</TH>
<TH>DSP 18x18</TH>
<TH>DSP 36x36</TH>
<TH>Pins</TH>
<TH>Virtual Pins</TH>
<TH>LUT-Only LCs</TH>
<TH>Register-Only LCs</TH>
<TH>LUT/Register LCs</TH>
<TH>Carry Chain LCs</TH>
<TH>Packed LCs</TH>
<TH>Full Hierarchy Name</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">|we</TD>
<TD ALIGN="LEFT">19 (0)</TD>
<TD ALIGN="LEFT">8</TD>
<TD ALIGN="LEFT">1024</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">8</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">11 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">8 (0)</TD>
<TD ALIGN="LEFT">7 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">|we</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> |NoteTabs:inst3|</TD>
<TD ALIGN="LEFT">11 (11)</TD>
<TD ALIGN="LEFT">8</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">3 (3)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">8 (8)</TD>
<TD ALIGN="LEFT">7 (7)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">|we|NoteTabs:inst3</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> |TONETABA:inst2|</TD>
<TD ALIGN="LEFT">8 (8)</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">8 (8)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">|we|TONETABA:inst2</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> |lpm_rom0:inst|</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">1024</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">|we|lpm_rom0:inst</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> |altsyncram:altsyncram_component|</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">1024</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">|we|lpm_rom0:inst|altsyncram:altsyncram_component</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> |altsyncram_f431:auto_generated|</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">1024</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">|we|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated</TD>
</TR>
</TABLE>
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.<br>
<P><A NAME="12"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Analysis & Synthesis RAM Summary</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Name</TH>
<TH>Type</TH>
<TH>Mode</TH>
<TH>Port A Depth</TH>
<TH>Port A Width</TH>
<TH>Port B Depth</TH>
<TH>Port B Width</TH>
<TH>Size</TH>
<TH>MIF</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|ALTSYNCRAM</TD>
<TD ALIGN="LEFT">AUTO</TD>
<TD ALIGN="LEFT">ROM</TD>
<TD ALIGN="LEFT">256</TD>
<TD ALIGN="LEFT">4</TD>
<TD ALIGN="LEFT">--</TD>
<TD ALIGN="LEFT">--</TD>
<TD ALIGN="LEFT">1024</TD>
<TD ALIGN="LEFT">YINYUE.mif</TD>
</TR>
</TABLE>
<P><A NAME="13"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>User-Specified and Inferred Latches</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Latch Name</TH>
<TH>Latch Enable Signal</TH>
<TH>Free of Timing Hazards</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">TONETABA:inst2|HIGH</TD>
<TD ALIGN="LEFT">TONETABA:inst2|Mux4</TD>
<TD ALIGN="LEFT">yes</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">TONETABA:inst2|CODE[2]</TD>
<TD ALIGN="LEFT">TONETABA:inst2|Mux4</TD>
<TD ALIGN="LEFT">yes</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">TONETABA:inst2|CODE[1]</TD>
<TD ALIGN="LEFT">TONETABA:inst2|Mux4</TD>
<TD ALIGN="LEFT">yes</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">TONETABA:inst2|CODE[0]</TD>
<TD ALIGN="LEFT">TONETABA:inst2|Mux4</TD>
<TD ALIGN="LEFT">yes</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Number of user-specified and inferred latches = 4 </TD>
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
</TR>
</TABLE>
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.<br>
<P><A NAME="14"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>General Register Statistics</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Statistic</TH>
<TH>Value</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total registers</TD>
<TD ALIGN="LEFT">8</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Number of registers using Synchronous Clear</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Number of registers using Synchronous Load</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Number of registers using Asynchronous Clear</TD>
<TD ALIGN="LEFT">8</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Number of registers using Asynchronous Load</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Number of registers using Clock Enable</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Number of registers using Preset</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
</TABLE>
<P><A NAME="15"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Source assignments for lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Assignment</TH>
<TH>Value</TH>
<TH>From</TH>
<TH>To</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">OPTIMIZE_POWER_DURING_SYNTHESIS</TD>
<TD ALIGN="LEFT">NORMAL_COMPILATION</TD>
<TD ALIGN="LEFT">-</TD>
<TD ALIGN="LEFT">-</TD>
</TR>
</TABLE>
<P><A NAME="16"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Parameter Settings for User Entity Instance: lpm_rom0:inst|altsyncram:altsyncram_component</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Parameter Name</TH>
<TH>Value</TH>
<TH>Type</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">BYTE_SIZE_BLOCK</TD>
<TD ALIGN="LEFT">8</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">AUTO_CARRY_CHAINS</TD>
<TD ALIGN="LEFT">ON</TD>
<TD ALIGN="LEFT">AUTO_CARRY</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">IGNORE_CARRY_BUFFERS</TD>
<TD ALIGN="LEFT">OFF</TD>
<TD ALIGN="LEFT">IGNORE_CARRY</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">AUTO_CASCADE_CHAINS</TD>
<TD ALIGN="LEFT">ON</TD>
<TD ALIGN="LEFT">AUTO_CASCADE</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">IGNORE_CASCADE_BUFFERS</TD>
<TD ALIGN="LEFT">OFF</TD>
<TD ALIGN="LEFT">IGNORE_CASCADE</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">OPERATION_MODE</TD>
<TD ALIGN="LEFT">ROM</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">WIDTH_A</TD>
<TD ALIGN="LEFT">4</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">WIDTHAD_A</TD>
<TD ALIGN="LEFT">8</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">NUMWORDS_A</TD>
<TD ALIGN="LEFT">256</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">OUTDATA_REG_A</TD>
<TD ALIGN="LEFT">CLOCK0</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">ADDRESS_ACLR_A</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">OUTDATA_ACLR_A</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">WRCONTROL_ACLR_A</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">INDATA_ACLR_A</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">BYTEENA_ACLR_A</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">WIDTH_B</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">WIDTHAD_B</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">NUMWORDS_B</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">INDATA_REG_B</TD>
<TD ALIGN="LEFT">CLOCK1</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">WRCONTROL_WRADDRESS_REG_B</TD>
<TD ALIGN="LEFT">CLOCK1</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">RDCONTROL_REG_B</TD>
<TD ALIGN="LEFT">CLOCK1</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">ADDRESS_REG_B</TD>
<TD ALIGN="LEFT">CLOCK1</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">OUTDATA_REG_B</TD>
<TD ALIGN="LEFT">UNREGISTERED</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">BYTEENA_REG_B</TD>
<TD ALIGN="LEFT">CLOCK1</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">INDATA_ACLR_B</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">WRCONTROL_ACLR_B</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">ADDRESS_ACLR_B</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">OUTDATA_ACLR_B</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">RDCONTROL_ACLR_B</TD>
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