we.cmp.rpt.htm

来自「出血FPGA,用VHDL做的音乐盒」· HTM 代码 · 共 2,084 行 · 第 1/5 页

<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">BYTEENA_ACLR_B</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">WIDTH_BYTEENA_A</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">WIDTH_BYTEENA_B</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">RAM_BLOCK_TYPE</TD>
<TD ALIGN="LEFT">AUTO</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">BYTE_SIZE</TD>
<TD ALIGN="LEFT">8</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">READ_DURING_WRITE_MODE_MIXED_PORTS</TD>
<TD ALIGN="LEFT">DONT_CARE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">INIT_FILE</TD>
<TD ALIGN="LEFT">YINYUE.mif</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">INIT_FILE_LAYOUT</TD>
<TD ALIGN="LEFT">PORT_A</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">MAXIMUM_DEPTH</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">CLOCK_ENABLE_INPUT_A</TD>
<TD ALIGN="LEFT">NORMAL</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">CLOCK_ENABLE_INPUT_B</TD>
<TD ALIGN="LEFT">NORMAL</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">CLOCK_ENABLE_OUTPUT_A</TD>
<TD ALIGN="LEFT">NORMAL</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">CLOCK_ENABLE_OUTPUT_B</TD>
<TD ALIGN="LEFT">NORMAL</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">DEVICE_FAMILY</TD>
<TD ALIGN="LEFT">Stratix</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">CBXI_PARAMETER</TD>
<TD ALIGN="LEFT">altsyncram_f431</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
</TABLE>
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".<br>
<P><A NAME="17"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Analysis & Synthesis Equations</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<a href="file:///D:/PLD/FPGAlicheng/music/we.map.eqn.htm">Analysis & Synthesis Equations</a><BR>
<P><A NAME="18"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Analysis & Synthesis Messages</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<PRE>
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Sep 23 20:21:50 2008
Info: Command: quartus_map --lower_priority --read_settings_files=on --write_settings_files=off we -c we
Info: Found 2 design units, including 1 entities, in source file SHUKONGDIV.vhd
    Info: Found design unit 1: SHUKONG_DIV-MA
    Info: Found entity 1: SHUKONG_DIV
Info: Found 2 design units, including 1 entities, in source file SPEAKER.vhd
    Info: Found design unit 1: SPEAKER-MA
    Info: Found entity 1: SPEAKER
Info: Found 1 design units, including 1 entities, in source file we.bdf
    Info: Found entity 1: we
Info: Found 2 design units, including 1 entities, in source file TONETABA.vhd
    Info: Found design unit 1: TONETABA-MA
    Info: Found entity 1: TONETABA
Info: Found 2 design units, including 1 entities, in source file NoteTabs.vhd
    Info: Found design unit 1: NoteTabs-one
    Info: Found entity 1: NoteTabs
Warning: Can't analyze file -- file D:/PLD/FPGAlicheng/music/lpm_rom1.tdf is missing
Info: Found 1 design units, including 1 entities, in source file lpm_rom0.tdf
    Info: Found entity 1: lpm_rom0
Info: Elaborating entity "we" for the top level hierarchy
Info: Elaborating entity "TONETABA" for hierarchy "TONETABA:inst2"
Warning (10631): VHDL Process Statement warning at TONETABA.vhd(12): inferring latch(es) for signal or variable "TONE", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at TONETABA.vhd(12): inferring latch(es) for signal or variable "CODE", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at TONETABA.vhd(12): inferring latch(es) for signal or variable "HIGH", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "HIGH"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "CODE[0]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "CODE[1]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "CODE[2]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "CODE[3]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[0]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[1]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[2]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[3]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[4]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[5]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[6]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[7]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[8]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[9]"
Info (10041): Verilog HDL or VHDL info at TONETABA.vhd(12): inferred latch for "TONE[10]"
Info: Elaborating entity "lpm_rom0" for hierarchy "lpm_rom0:inst"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "lpm_rom0:inst|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "lpm_rom0:inst|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_f431.tdf
    Info: Found entity 1: altsyncram_f431
Info: Elaborating entity "altsyncram_f431" for hierarchy "lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated"
Info: Elaborating entity "NoteTabs" for hierarchy "NoteTabs:inst3"
Info: Elaborating entity "SPEAKER" for hierarchy "SPEAKER:inst1"
Warning (10036): Verilog HDL or VHDL warning at SPEAKER.vhd(10): object "FULLSPKS" assigned a value but never read
Warning (10034): Output port "SPKS" at SPEAKER.vhd(7) has no driver
Warning: Entity "SPEAKER" contains only dangling pins
Warning: Latch TONETABA:inst2|HIGH has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[3]
Warning: Latch TONETABA:inst2|CODE[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[2]
Warning: Latch TONETABA:inst2|CODE[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[1]
Warning: Latch TONETABA:inst2|CODE[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated|q_a[0]
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "SPKS" stuck at GND
    Warning: Pin "CODE[3]" stuck at GND
Warning: Design contains 1 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "CLK12M"
Info: Implemented 31 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 6 output pins
    Info: Implemented 19 logic cells
    Info: Implemented 4 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 20 warnings
    Info: Processing ended: Tue Sep 23 20:21:51 2008
    Info: Elapsed time: 00:00:02
</PRE>
<P><A NAME="19"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Fitter Summary</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle">
<TD ALIGN="LEFT">Fitter Status</TH>
<TD ALIGN="LEFT">Successful - Tue Sep 23 20:21:59 2008</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Quartus II Version</TD>
<TD ALIGN="LEFT">6.0 Build 178 04/27/2006 SJ Full Version</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Revision Name</TD>
<TD ALIGN="LEFT">we</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Top-level Entity Name</TD>
<TD ALIGN="LEFT">we</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Family</TD>
<TD ALIGN="LEFT">Stratix</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Device</TD>
<TD ALIGN="LEFT">EP1S10F484C5</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Timing Models</TD>
<TD ALIGN="LEFT">Final</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total logic elements</TD>
<TD ALIGN="LEFT">20 / 10,570 ( < 1 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total pins</TD>
<TD ALIGN="LEFT">8 / 336 ( 2 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total virtual pins</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total memory bits</TD>
<TD ALIGN="LEFT">1,024 / 920,448 ( < 1 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">DSP block 9-bit elements</TD>
<TD ALIGN="LEFT">0 / 48 ( 0 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total PLLs</TD>
<TD ALIGN="LEFT">0 / 6 ( 0 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total DLLs</TD>
<TD ALIGN="LEFT">0 / 2 ( 0 % )</TD>
</TR>
</TABLE>
<P><A NAME="20"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Fitter Settings</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Option</TH>
<TH>Setting</TH>
<TH>Default Value</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Device</TD>
<TD ALIGN="LEFT">AUTO</TD>
<TD ALIGN="LEFT">&nbsp;</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Use smart compilation</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Router Timing Optimization Level</TD>
<TD ALIGN="LEFT">Normal</TD>
<TD ALIGN="LEFT">Normal</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Placement Effort Multiplier</TD>
<TD ALIGN="LEFT">1.0</TD>
<TD ALIGN="LEFT">1.0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Router Effort Multiplier</TD>
<TD ALIGN="LEFT">1.0</TD>
<TD ALIGN="LEFT">1.0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Optimize Hold Timing</TD>
<TD ALIGN="LEFT">IO Paths and Minimum TPD Paths</TD>
<TD ALIGN="LEFT">IO Paths and Minimum TPD Paths</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Optimize Fast-Corner Timing</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Optimize Timing</TD>
<TD ALIGN="LEFT">Normal compilation</TD>
<TD ALIGN="LEFT">Normal compilation</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Optimize IOC Register Placement for Timing</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Limit to One Fitting Attempt</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Final Placement Optimizations</TD>
<TD ALIGN="LEFT">Automatically</TD>
<TD ALIGN="LEFT">Automatically</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Fitter Aggressive Routability Optimizations</TD>
<TD ALIGN="LEFT">Automatically</TD>
<TD ALIGN="LEFT">Automatically</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Fitter Initial Placement Seed</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">1</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Slow Slew Rate</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">PCI I/O</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Weak Pull-Up Resistor</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Enable Bus-Hold Circuitry</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Global Memory Control Signals</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Packed Registers -- Stratix/Stratix GX</TD>
<TD ALIGN="LEFT">Auto</TD>
<TD ALIGN="LEFT">Auto</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Delay Chains</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Merge PLLs</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Perform Physical Synthesis for Combinational Logic</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Perform Register Duplication</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Perform Register Retiming</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Perform Asynchronous Signal Pipelining</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Fitter Effort</TD>
<TD ALIGN="LEFT">Auto Fit</TD>
<TD ALIGN="LEFT">Auto Fit</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Physical Synthesis Effort Level</TD>
<TD ALIGN="LEFT">Normal</TD>
<TD ALIGN="LEFT">Normal</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Logic Cell Insertion - Logic Duplication</TD>
<TD ALIGN="LEFT">Auto</TD>
<TD ALIGN="LEFT">Auto</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Register Duplication</TD>
<TD ALIGN="LEFT">Auto</TD>
<TD ALIGN="LEFT">Auto</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Global Clock</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Global Register Control Signals</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
</TABLE>
<P><A NAME="21"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Fitter Equations</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<a href="file:///D:/PLD/FPGAlicheng/music/we.fit.eqn.htm">Fitter Equations</a><BR>
<P><A NAME="22"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Pin-Out File</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<a href="file:///D:/PLD/FPGAlicheng/music/we.pin">Pin-Out File</a><BR>
<P><A NAME="23"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Fitter Resource Usage Summary</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Resource</TH>
<TH>Usage</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total logic elements</TD>