⭐ 欢迎来到虫虫下载站！ | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站
📤 上传资源

📄 we.cmp.rpt.htm

📁 出血FPGA,用VHDL做的音乐盒
💻 HTM
📖 第 1 页 / 共 5 页
字号:
🔍
12345 
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Ignore ROW GLOBAL Buffers</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Ignore LCELL Buffers</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Ignore SOFT Buffers</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Limit AHDL Integers to 32 Bits</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Optimization Technique -- Stratix/Stratix GX</TD>
<TD ALIGN="LEFT">Balanced</TD>
<TD ALIGN="LEFT">Balanced</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II</TD>
<TD ALIGN="LEFT">70</TD>
<TD ALIGN="LEFT">70</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Carry Chains</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Open-Drain Pins</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Remove Duplicate Logic</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Perform WYSIWYG Primitive Resynthesis</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Perform gate-level register retiming</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Allow register retiming to trade off Tsu/Tco with Fmax</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto ROM Replacement</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto RAM Replacement</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto DSP Block Replacement</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Shift Register Replacement</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Clock Enable Replacement</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Allow Synchronous Control Signals</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Force Use of Synchronous Clear Signals</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto RAM Block Balancing</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Resource Sharing</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Allow Any RAM Size For Recognition</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Allow Any ROM Size For Recognition</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Allow Any Shift Register Size For Recognition</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Maximum Number of M512 Memory Blocks</TD>
<TD ALIGN="LEFT">Unlimited</TD>
<TD ALIGN="LEFT">Unlimited</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Maximum Number of M4K Memory Blocks</TD>
<TD ALIGN="LEFT">Unlimited</TD>
<TD ALIGN="LEFT">Unlimited</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Maximum Number of M-RAM Memory Blocks</TD>
<TD ALIGN="LEFT">Unlimited</TD>
<TD ALIGN="LEFT">Unlimited</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Ignore translate_off and translate_on Synthesis Directives</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Show Parameter Settings Tables in Synthesis Report</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Ignore Maximum Fan-Out Assignments</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Retiming Meta-Stability Register Sequence Length</TD>
<TD ALIGN="LEFT">2</TD>
<TD ALIGN="LEFT">2</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">PowerPlay Power Optimization</TD>
<TD ALIGN="LEFT">Normal compilation</TD>
<TD ALIGN="LEFT">Normal compilation</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">HDL message level</TD>
<TD ALIGN="LEFT">Level2</TD>
<TD ALIGN="LEFT">Level2</TD>
</TR>
</TABLE>
<P><A NAME="9"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Analysis & Synthesis Source Files Read</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>File Name with User-Entered Path</TH>
<TH>Used in Netlist</TH>
<TH>File Type</TH>
<TH>File Name with Absolute Path</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">SPEAKER.vhd</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">User VHDL File </TD>
<TD ALIGN="LEFT">D:/PLD/FPGAlicheng/music/SPEAKER.vhd</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">we.bdf</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">User Block Diagram/Schematic File </TD>
<TD ALIGN="LEFT">D:/PLD/FPGAlicheng/music/we.bdf</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">TONETABA.vhd</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">User VHDL File </TD>
<TD ALIGN="LEFT">D:/PLD/FPGAlicheng/music/TONETABA.vhd</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">NoteTabs.vhd</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">User VHDL File </TD>
<TD ALIGN="LEFT">D:/PLD/FPGAlicheng/music/NoteTabs.vhd</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">lpm_rom0.tdf</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">User AHDL File </TD>
<TD ALIGN="LEFT">D:/PLD/FPGAlicheng/music/lpm_rom0.tdf</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">altsyncram.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/altera/quartus60/libraries/megafunctions/altsyncram.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">altsyncram.tdf</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Megafunction </TD>
<TD ALIGN="LEFT">c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">stratix_ram_block.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/altera/quartus60/libraries/megafunctions/stratix_ram_block.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">lpm_mux.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/altera/quartus60/libraries/megafunctions/lpm_mux.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">lpm_decode.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/altera/quartus60/libraries/megafunctions/lpm_decode.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">aglobal60.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/altera/quartus60/libraries/megafunctions/aglobal60.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">a_rdenreg.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/altera/quartus60/libraries/megafunctions/a_rdenreg.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">altrom.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/altera/quartus60/libraries/megafunctions/altrom.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">altram.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/altera/quartus60/libraries/megafunctions/altram.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">altdpram.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/altera/quartus60/libraries/megafunctions/altdpram.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">altqpram.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/altera/quartus60/libraries/megafunctions/altqpram.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">db/altsyncram_f431.tdf</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Auto-Generated Megafunction </TD>
<TD ALIGN="LEFT">D:/PLD/FPGAlicheng/music/db/altsyncram_f431.tdf</TD>
</TR>
</TABLE>
<P><A NAME="10"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Analysis & Synthesis Resource Usage Summary</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Resource</TH>
<TH>Usage</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total logic elements</TD>
<TD ALIGN="LEFT">19</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">&nbsp;&nbsp;&nbsp;&nbsp;-- Combinational with no register</TD>
<TD ALIGN="LEFT">11</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">&nbsp;&nbsp;&nbsp;&nbsp;-- Register only</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">&nbsp;&nbsp;&nbsp;&nbsp;-- Combinational with a register</TD>
<TD ALIGN="LEFT">8</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">&nbsp;</TD>
<TD ALIGN="LEFT">&nbsp;</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Logic element usage by number of LUT inputs</TD>
<TD ALIGN="LEFT">&nbsp;</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">&nbsp;&nbsp;&nbsp;&nbsp;-- 4 input functions</TD>
<TD ALIGN="LEFT">3</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">&nbsp;&nbsp;&nbsp;&nbsp;-- 3 input functions</TD>
<TD ALIGN="LEFT">7</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">&nbsp;&nbsp;&nbsp;&nbsp;-- 2 input functions</TD>
<TD ALIGN="LEFT">8</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">&nbsp;&nbsp;&nbsp;&nbsp;-- 1 input functions</TD>
<TD ALIGN="LEFT">1</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">&nbsp;&nbsp;&nbsp;&nbsp;-- 0 input functions</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;-- Combinational cells for routing</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">&nbsp;</TD>
<TD ALIGN="LEFT">&nbsp;</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Logic elements by mode</TD>
<TD ALIGN="LEFT">&nbsp;</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">&nbsp;&nbsp;&nbsp;&nbsp;-- normal mode</TD>
<TD ALIGN="LEFT">13</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">&nbsp;&nbsp;&nbsp;&nbsp;-- arithmetic mode</TD>
<TD ALIGN="LEFT">6</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">&nbsp;&nbsp;&nbsp;&nbsp;-- qfbk mode</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">&nbsp;&nbsp;&nbsp;&nbsp;-- register cascade mode</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">&nbsp;&nbsp;&nbsp;&nbsp;-- synchronous clear/load mode</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">&nbsp;&nbsp;&nbsp;&nbsp;-- asynchronous clear/load mode</TD>
<TD ALIGN="LEFT">8</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">&nbsp;</TD>
<TD ALIGN="LEFT">&nbsp;</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total registers</TD>
<TD ALIGN="LEFT">8</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total logic cells in carry chains</TD>
<TD ALIGN="LEFT">7</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">I/O pins</TD>
<TD ALIGN="LEFT">8</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total memory bits</TD>
<TD ALIGN="LEFT">1024</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Maximum fan-out node</TD>
<TD ALIGN="LEFT">CLK8Hz</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Maximum fan-out</TD>
<TD ALIGN="LEFT">12</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total fan-out</TD>
<TD ALIGN="LEFT">106</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Average fan-out</TD>
<TD ALIGN="LEFT">3.42</TD>
</TR>
</TABLE>
<P><A NAME="11"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Analysis & Synthesis Resource Utilization by Entity</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Compilation Hierarchy Node</TH>
<TH>Logic Cells</TH>
<TH>LC Registers</TH>
<TH>Memory Bits</TH>
12345

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -