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📁 出血FPGA,用VHDL做的音乐盒
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<TITLE>Compilation report for we</TITLE>
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<H1>Compilation report for we</H1>
<H3>Tue Sep 23 20:22:06 2008<BR>
Version 6.0 Build 178 04/27/2006 SJ Full Version</H3>
</CENTER>

<P><HR></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Table of Contents</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<OL>
<LI><A HREF="#1">Legal Notice</A></LI>
<LI><A HREF="#2">Flow Summary</A></LI>
<LI><A HREF="#3">Flow Settings</A></LI>
<LI><A HREF="#4">Flow Non-Default Global Settings</A></LI>
<LI><A HREF="#5">Flow Elapsed Time</A></LI>
<LI><A HREF="#6">Flow Log</A></LI>
<LI><A HREF="#7">Analysis & Synthesis Summary</A></LI>
<LI><A HREF="#8">Analysis & Synthesis Settings</A></LI>
<LI><A HREF="#9">Analysis & Synthesis Source Files Read</A></LI>
<LI><A HREF="#10">Analysis & Synthesis Resource Usage Summary</A></LI>
<LI><A HREF="#11">Analysis & Synthesis Resource Utilization by Entity</A></LI>
<LI><A HREF="#12">Analysis & Synthesis RAM Summary</A></LI>
<LI><A HREF="#13">User-Specified and Inferred Latches</A></LI>
<LI><A HREF="#14">General Register Statistics</A></LI>
<LI><A HREF="#15">Source assignments for lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_f431:auto_generated</A></LI>
<LI><A HREF="#16">Parameter Settings for User Entity Instance: lpm_rom0:inst|altsyncram:altsyncram_component</A></LI>
<LI><A HREF="#17">Analysis & Synthesis Equations</A></LI>
<LI><A HREF="#18">Analysis & Synthesis Messages</A></LI>
<LI><A HREF="#19">Fitter Summary</A></LI>
<LI><A HREF="#20">Fitter Settings</A></LI>
<LI><A HREF="#21">Fitter Equations</A></LI>
<LI><A HREF="#22">Pin-Out File</A></LI>
<LI><A HREF="#23">Fitter Resource Usage Summary</A></LI>
<LI><A HREF="#24">Input Pins</A></LI>
<LI><A HREF="#25">Output Pins</A></LI>
<LI><A HREF="#26">I/O Bank Usage</A></LI>
<LI><A HREF="#27">All Package Pins</A></LI>
<LI><A HREF="#28">Output Pin Default Load For Reported TCO</A></LI>
<LI><A HREF="#29">Fitter Resource Utilization by Entity</A></LI>
<LI><A HREF="#30">Delay Chain Summary</A></LI>
<LI><A HREF="#31">Pad To Core Delay Chain Fanout</A></LI>
<LI><A HREF="#32">Control Signals</A></LI>
<LI><A HREF="#33">Global & Other Fast Signals</A></LI>
<LI><A HREF="#34">Non-Global High Fan-Out Signals</A></LI>
<LI><A HREF="#35">Fitter RAM Summary</A></LI>
<LI><A HREF="#36">Interconnect Usage Summary</A></LI>
<LI><A HREF="#37">LAB Logic Elements</A></LI>
<LI><A HREF="#38">LAB-wide Signals</A></LI>
<LI><A HREF="#39">LAB Signals Sourced</A></LI>
<LI><A HREF="#40">LAB Signals Sourced Out</A></LI>
<LI><A HREF="#41">LAB Distinct Inputs</A></LI>
<LI><A HREF="#42">Fitter Device Options</A></LI>
<LI><A HREF="#43">Advanced Data - General</A></LI>
<LI><A HREF="#44">Advanced Data - Placement Preparation</A></LI>
<LI><A HREF="#45">Advanced Data - Placement</A></LI>
<LI><A HREF="#46">Advanced Data - Routing</A></LI>
<LI><A HREF="#47">Fitter Messages</A></LI>
<LI><A HREF="#48">Fitter Suppressed Messages</A></LI>
<LI><A HREF="#49">Assembler Summary</A></LI>
<LI><A HREF="#50">Assembler Settings</A></LI>
<LI><A HREF="#51">Assembler Generated Files</A></LI>
<LI><A HREF="#52">Assembler Device Options: D:/PLD/FPGAlicheng/music/we.sof</A></LI>
<LI><A HREF="#53">Assembler Device Options: D:/PLD/FPGAlicheng/music/we.pof</A></LI>
<LI><A HREF="#54">Assembler Messages</A></LI>
<LI><A HREF="#55">Timing Analyzer Summary</A></LI>
<LI><A HREF="#56">Timing Analyzer Settings</A></LI>
<LI><A HREF="#57">Clock Settings Summary</A></LI>
<LI><A HREF="#58">Clock Setup: 'CLK8Hz'</A></LI>
<LI><A HREF="#59">Clock Hold: 'CLK8Hz'</A></LI>
<LI><A HREF="#60">tco</A></LI>
<LI><A HREF="#61">Timing Analyzer Messages</A></LI>
</OL>

<P><A NAME="1"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Legal Notice</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<PRE>Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
</PRE>

<P><A NAME="2"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Flow Summary</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle">
<TD ALIGN="LEFT">Flow Status</TH>
<TD ALIGN="LEFT">Successful - Tue Sep 23 20:22:06 2008</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Quartus II Version</TD>
<TD ALIGN="LEFT">6.0 Build 178 04/27/2006 SJ Full Version</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Revision Name</TD>
<TD ALIGN="LEFT">we</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Top-level Entity Name</TD>
<TD ALIGN="LEFT">we</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Family</TD>
<TD ALIGN="LEFT">Stratix</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Met timing requirements</TD>
<TD ALIGN="LEFT">No</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total logic elements</TD>
<TD ALIGN="LEFT">20 / 10,570 ( < 1 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total pins</TD>
<TD ALIGN="LEFT">8 / 336 ( 2 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total virtual pins</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total memory bits</TD>
<TD ALIGN="LEFT">1,024 / 920,448 ( < 1 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">DSP block 9-bit elements</TD>
<TD ALIGN="LEFT">0 / 48 ( 0 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total PLLs</TD>
<TD ALIGN="LEFT">0 / 6 ( 0 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total DLLs</TD>
<TD ALIGN="LEFT">0 / 2 ( 0 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Device</TD>
<TD ALIGN="LEFT">EP1S10F484C5</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Timing Models</TD>
<TD ALIGN="LEFT">Final</TD>
</TR>
</TABLE>
<P><A NAME="3"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Flow Settings</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Option</TH>
<TH>Setting</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Start date & time</TD>
<TD ALIGN="LEFT">09/23/2008 20:21:50</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Main task</TD>
<TD ALIGN="LEFT">Compilation</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Revision Name</TD>
<TD ALIGN="LEFT">we</TD>
</TR>
</TABLE>
<P><A NAME="4"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Flow Non-Default Global Settings</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Assignment Name</TH>
<TH>Value</TH>
<TH>Default Value</TH>
<TH>Entity Name</TH>
<TH>Section Id</TH>
</TR>
</TABLE>
<P><A NAME="5"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Flow Elapsed Time</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Module Name</TH>
<TH>Elapsed Time</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Analysis & Synthesis</TD>
<TD ALIGN="LEFT">00:00:02</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Fitter</TD>
<TD ALIGN="LEFT">00:00:06</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Assembler</TD>
<TD ALIGN="LEFT">00:00:03</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Timing Analyzer</TD>
<TD ALIGN="LEFT">00:00:01</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total</TD>
<TD ALIGN="LEFT">00:00:12</TD>
</TR>
</TABLE>
<P><A NAME="6"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Flow Log</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<PRE>quartus_map --lower_priority --read_settings_files=on --write_settings_files=off we -c we
quartus_fit --lower_priority --read_settings_files=off --write_settings_files=off we -c we
quartus_asm --lower_priority --read_settings_files=off --write_settings_files=off we -c we
quartus_tan --lower_priority --read_settings_files=off --write_settings_files=off we -c we --timing_analysis_only
</PRE>

<P><A NAME="7"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Analysis & Synthesis Summary</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle">
<TD ALIGN="LEFT">Analysis & Synthesis Status</TH>
<TD ALIGN="LEFT">Successful - Tue Sep 23 20:21:51 2008</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Quartus II Version</TD>
<TD ALIGN="LEFT">6.0 Build 178 04/27/2006 SJ Full Version</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Revision Name</TD>
<TD ALIGN="LEFT">we</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Top-level Entity Name</TD>
<TD ALIGN="LEFT">we</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Family</TD>
<TD ALIGN="LEFT">Stratix</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total logic elements</TD>
<TD ALIGN="LEFT">19</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total pins</TD>
<TD ALIGN="LEFT">8</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total virtual pins</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total memory bits</TD>
<TD ALIGN="LEFT">1,024</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">DSP block 9-bit elements</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total PLLs</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total DLLs</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
</TABLE>
<P><A NAME="8"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Analysis & Synthesis Settings</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Option</TH>
<TH>Setting</TH>
<TH>Default Value</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Top-level entity name</TD>
<TD ALIGN="LEFT">we</TD>
<TD ALIGN="LEFT">we</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Family name</TD>
<TD ALIGN="LEFT">Stratix</TD>
<TD ALIGN="LEFT">Stratix</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Use smart compilation</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Restructure Multiplexers</TD>
<TD ALIGN="LEFT">Auto</TD>
<TD ALIGN="LEFT">Auto</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Create Debugging Nodes for IP Cores</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Preserve fewer node names</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Disable OpenCore Plus hardware evaluation</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Verilog Version</TD>
<TD ALIGN="LEFT">Verilog_2001</TD>
<TD ALIGN="LEFT">Verilog_2001</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">VHDL Version</TD>
<TD ALIGN="LEFT">VHDL93</TD>
<TD ALIGN="LEFT">VHDL93</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">State Machine Processing</TD>
<TD ALIGN="LEFT">Auto</TD>
<TD ALIGN="LEFT">Auto</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Extract Verilog State Machines</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Extract VHDL State Machines</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Add Pass-Through Logic to Inferred RAMs</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">DSP Block Balancing</TD>
<TD ALIGN="LEFT">Auto</TD>
<TD ALIGN="LEFT">Auto</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Maximum DSP Block Usage</TD>
<TD ALIGN="LEFT">Unlimited</TD>
<TD ALIGN="LEFT">Unlimited</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">NOT Gate Push-Back</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Power-Up Don't Care</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Remove Redundant Logic Cells</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Remove Duplicate Registers</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Ignore CARRY Buffers</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Ignore CASCADE Buffers</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Ignore GLOBAL Buffers</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
12345

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