📄 clock.rpt
字号:
clock
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - A 22 SOFT s ! 1 0 0 5 clr~1
- 5 - A 16 AND2 0 2 0 3 |COUNT24:1|LPM_ADD_SUB:47|addcore:adder|:55
- 5 - C 13 AND2 0 2 0 1 |COUNT24:1|LPM_ADD_SUB:171|addcore:adder|:55
- 6 - C 13 OR2 0 4 0 1 |COUNT24:1|LPM_ADD_SUB:171|addcore:adder|:69
- 3 - A 16 DFFE + 0 3 0 4 |COUNT24:1|cin (|COUNT24:1|:14)
- 8 - A 16 DFFE + 0 3 1 1 |COUNT24:1|cnt03 (|COUNT24:1|:17)
- 7 - A 16 DFFE + 0 3 1 2 |COUNT24:1|cnt02 (|COUNT24:1|:18)
- 1 - A 16 DFFE + 0 3 1 1 |COUNT24:1|cnt01 (|COUNT24:1|:19)
- 4 - A 16 DFFE + 0 1 1 2 |COUNT24:1|cnt00 (|COUNT24:1|:20)
- 6 - A 16 AND2 0 3 0 3 |COUNT24:1|:36
- 2 - C 13 DFFE + 0 3 1 2 |COUNT24:1|cnt13 (|COUNT24:1|:141)
- 7 - C 13 DFFE + 0 3 1 2 |COUNT24:1|cnt12 (|COUNT24:1|:142)
- 1 - C 13 DFFE + 0 3 1 3 |COUNT24:1|cnt11 (|COUNT24:1|:143)
- 4 - C 13 DFFE + 0 2 1 4 |COUNT24:1|cnt10 (|COUNT24:1|:144)
- 3 - C 13 OR2 ! 0 4 0 4 |COUNT24:1|:160
- 5 - C 10 AND2 0 2 0 1 |COUNT60:2|LPM_ADD_SUB:47|addcore:adder|:55
- 7 - C 10 OR2 0 4 0 1 |COUNT60:2|LPM_ADD_SUB:47|addcore:adder|:69
- 6 - B 09 AND2 0 2 0 1 |COUNT60:2|LPM_ADD_SUB:171|addcore:adder|:55
- 7 - B 09 OR2 0 4 0 1 |COUNT60:2|LPM_ADD_SUB:171|addcore:adder|:69
- 3 - B 09 DFFE + 0 3 0 5 |COUNT60:2|:1
- 2 - C 10 DFFE + 1 2 0 5 |COUNT60:2|cin (|COUNT60:2|:14)
- 6 - C 10 DFFE + 1 2 1 2 |COUNT60:2|cnt03 (|COUNT60:2|:17)
- 3 - C 10 DFFE + 1 2 1 2 |COUNT60:2|cnt02 (|COUNT60:2|:18)
- 1 - C 10 DFFE + 1 2 1 3 |COUNT60:2|cnt01 (|COUNT60:2|:19)
- 8 - C 10 DFFE + 1 0 1 4 |COUNT60:2|cnt00 (|COUNT60:2|:20)
- 4 - C 10 AND2 0 4 0 4 |COUNT60:2|:36
- 1 - B 09 DFFE + 0 3 1 2 |COUNT60:2|cnt13 (|COUNT60:2|:141)
- 8 - B 09 DFFE + 0 3 1 2 |COUNT60:2|cnt12 (|COUNT60:2|:142)
- 4 - B 09 DFFE + 0 3 1 3 |COUNT60:2|cnt11 (|COUNT60:2|:143)
- 2 - B 09 DFFE + 0 1 1 4 |COUNT60:2|cnt10 (|COUNT60:2|:144)
- 5 - B 09 AND2 0 4 0 4 |COUNT60:2|:160
- 6 - B 21 AND2 0 2 0 1 |COUNT60:3|LPM_ADD_SUB:47|addcore:adder|:55
- 8 - B 21 OR2 0 4 0 1 |COUNT60:3|LPM_ADD_SUB:47|addcore:adder|:69
- 2 - A 21 AND2 0 2 0 1 |COUNT60:3|LPM_ADD_SUB:171|addcore:adder|:55
- 6 - A 21 OR2 0 4 0 1 |COUNT60:3|LPM_ADD_SUB:171|addcore:adder|:69
- 2 - A 16 DFFE + 0 3 0 5 |COUNT60:3|:1
- 2 - B 21 DFFE + 0 3 0 5 |COUNT60:3|cin (|COUNT60:3|:14)
- 1 - B 21 DFFE + 0 3 1 2 |COUNT60:3|cnt03 (|COUNT60:3|:17)
- 3 - B 21 DFFE + 0 3 1 2 |COUNT60:3|cnt02 (|COUNT60:3|:18)
- 7 - B 21 DFFE + 0 3 1 3 |COUNT60:3|cnt01 (|COUNT60:3|:19)
- 5 - B 21 DFFE + 0 1 1 4 |COUNT60:3|cnt00 (|COUNT60:3|:20)
- 4 - B 21 AND2 0 4 0 4 |COUNT60:3|:36
- 4 - A 21 DFFE + 0 3 1 2 |COUNT60:3|cnt13 (|COUNT60:3|:141)
- 8 - A 21 DFFE + 0 3 1 2 |COUNT60:3|cnt12 (|COUNT60:3|:142)
- 1 - A 21 DFFE + 0 3 1 3 |COUNT60:3|cnt11 (|COUNT60:3|:143)
- 3 - A 21 DFFE + 0 1 1 4 |COUNT60:3|cnt10 (|COUNT60:3|:144)
- 5 - A 21 AND2 0 4 0 4 |COUNT60:3|:160
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\clock\clock.rpt
clock
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 3/ 96( 3%) 0/ 48( 0%) 7/ 48( 14%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
B: 3/ 96( 3%) 4/ 48( 8%) 4/ 48( 8%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
C: 2/ 96( 2%) 4/ 48( 8%) 4/ 48( 8%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\clock\clock.rpt
clock
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 29 clk
Device-Specific Information: f:\clock\clock.rpt
clock
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 25 clr
Device-Specific Information: f:\clock\clock.rpt
clock
** EQUATIONS **
clk : INPUT;
clr : INPUT;
en : INPUT;
-- Node name is 'clr~1'
-- Equation name is 'clr~1', location is LC2_A22, type is buried.
-- synthesized logic cell
!_LC2_A22 = _LC2_A22~NOT;
_LC2_A22~NOT = LCELL(!clr);
-- Node name is 'one0'
-- Equation name is 'one0', type is output
one0 = _LC4_A16;
-- Node name is 'one1'
-- Equation name is 'one1', type is output
one1 = _LC1_A16;
-- Node name is 'one2'
-- Equation name is 'one2', type is output
one2 = _LC7_A16;
-- Node name is 'one3'
-- Equation name is 'one3', type is output
one3 = _LC8_A16;
-- Node name is 'q10'
-- Equation name is 'q10', type is output
q10 = _LC8_C10;
-- Node name is 'q11'
-- Equation name is 'q11', type is output
q11 = _LC1_C10;
-- Node name is 'q12'
-- Equation name is 'q12', type is output
q12 = _LC3_C10;
-- Node name is 'q13'
-- Equation name is 'q13', type is output
q13 = _LC6_C10;
-- Node name is 'q20'
-- Equation name is 'q20', type is output
q20 = _LC2_B9;
-- Node name is 'q21'
-- Equation name is 'q21', type is output
q21 = _LC4_B9;
-- Node name is 'q22'
-- Equation name is 'q22', type is output
q22 = _LC8_B9;
-- Node name is 'q23'
-- Equation name is 'q23', type is output
q23 = _LC1_B9;
-- Node name is 'q30'
-- Equation name is 'q30', type is output
q30 = _LC5_B21;
-- Node name is 'q31'
-- Equation name is 'q31', type is output
q31 = _LC7_B21;
-- Node name is 'q32'
-- Equation name is 'q32', type is output
q32 = _LC3_B21;
-- Node name is 'q33'
-- Equation name is 'q33', type is output
q33 = _LC1_B21;
-- Node name is 'q40'
-- Equation name is 'q40', type is output
q40 = _LC3_A21;
-- Node name is 'q41'
-- Equation name is 'q41', type is output
q41 = _LC1_A21;
-- Node name is 'q42'
-- Equation name is 'q42', type is output
q42 = _LC8_A21;
-- Node name is 'q43'
-- Equation name is 'q43', type is output
q43 = _LC4_A21;
-- Node name is 'ten0'
-- Equation name is 'ten0', type is output
ten0 = _LC4_C13;
-- Node name is 'ten1'
-- Equation name is 'ten1', type is output
ten1 = _LC1_C13;
-- Node name is 'ten2'
-- Equation name is 'ten2', type is output
ten2 = _LC7_C13;
-- Node name is 'ten3'
-- Equation name is 'ten3', type is output
ten3 = _LC2_C13;
-- Node name is '|COUNT24:1|:14' = '|COUNT24:1|cin'
-- Equation name is '_LC3_A16', type is buried
_LC3_A16 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, !_LC2_A22);
_EQ001 = _LC2_A16 & _LC6_A16
# !_LC2_A16 & _LC3_A16;
-- Node name is '|COUNT24:1|:20' = '|COUNT24:1|cnt00'
-- Equation name is '_LC4_A16', type is buried
_LC4_A16 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ002 = !_LC2_A16 & _LC4_A16
# _LC2_A16 & !_LC4_A16;
-- Node name is '|COUNT24:1|:19' = '|COUNT24:1|cnt01'
-- Equation name is '_LC1_A16', type is buried
_LC1_A16 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ003 = _LC1_A16 & !_LC4_A16 & !_LC6_A16
# !_LC1_A16 & _LC2_A16 & _LC4_A16 & !_LC6_A16
# _LC1_A16 & !_LC2_A16;
-- Node name is '|COUNT24:1|:18' = '|COUNT24:1|cnt02'
-- Equation name is '_LC7_A16', type is buried
_LC7_A16 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ004 = !_LC5_A16 & !_LC6_A16 & _LC7_A16
# _LC2_A16 & _LC5_A16 & !_LC6_A16 & !_LC7_A16
# !_LC2_A16 & _LC7_A16;
-- Node name is '|COUNT24:1|:17' = '|COUNT24:1|cnt03'
-- Equation name is '_LC8_A16', type is buried
_LC8_A16 = DFFE( _EQ005, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ005 = !_LC7_A16 & _LC8_A16
# !_LC5_A16 & _LC8_A16
# _LC2_A16 & _LC5_A16 & _LC7_A16 & !_LC8_A16
# !_LC2_A16 & _LC8_A16;
-- Node name is '|COUNT24:1|:144' = '|COUNT24:1|cnt10'
-- Equation name is '_LC4_C13', type is buried
_LC4_C13 = DFFE( _EQ006, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ006 = _LC3_A16 & !_LC3_C13 & !_LC4_C13
# !_LC3_A16 & _LC4_C13;
-- Node name is '|COUNT24:1|:143' = '|COUNT24:1|cnt11'
-- Equation name is '_LC1_C13', type is buried
_LC1_C13 = DFFE( _EQ007, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ007 = _LC1_C13 & !_LC3_C13 & !_LC4_C13
# !_LC1_C13 & _LC3_A16 & !_LC3_C13 & _LC4_C13
# _LC1_C13 & !_LC3_A16;
-- Node name is '|COUNT24:1|:142' = '|COUNT24:1|cnt12'
-- Equation name is '_LC7_C13', type is buried
_LC7_C13 = DFFE( _EQ008, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ008 = !_LC3_C13 & !_LC5_C13 & _LC7_C13
# _LC3_A16 & !_LC3_C13 & _LC5_C13 & !_LC7_C13
# !_LC3_A16 & _LC7_C13;
-- Node name is '|COUNT24:1|:141' = '|COUNT24:1|cnt13'
-- Equation name is '_LC2_C13', type is buried
_LC2_C13 = DFFE( _EQ009, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ009 = _LC3_A16 & !_LC3_C13 & _LC6_C13
# _LC2_C13 & !_LC3_A16;
-- Node name is '|COUNT24:1|LPM_ADD_SUB:47|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A16', type is buried
_LC5_A16 = LCELL( _EQ010);
_EQ010 = _LC1_A16 & _LC4_A16;
-- Node name is '|COUNT24:1|LPM_ADD_SUB:171|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C13', type is buried
_LC5_C13 = LCELL( _EQ011);
_EQ011 = _LC1_C13 & _LC4_C13;
-- Node name is '|COUNT24:1|LPM_ADD_SUB:171|addcore:adder|:69' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC6_C13', type is buried
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