📄 count24.rpt
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Device-Specific Information: f:\clock\count24.rpt
count24
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 5/ 96( 5%) 0/ 48( 0%) 6/ 48( 12%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\clock\count24.rpt
count24
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 10 clk
Device-Specific Information: f:\clock\count24.rpt
count24
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 9 clr
Device-Specific Information: f:\clock\count24.rpt
count24
** EQUATIONS **
clk : INPUT;
clr : INPUT;
en : INPUT;
-- Node name is ':14' = 'cin'
-- Equation name is 'cin', location is LC8_A18, type is buried.
cin = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, !_LC2_A18);
_EQ001 = en & _LC7_A18
# cin & !en;
-- Node name is 'clr~1'
-- Equation name is 'clr~1', location is LC2_A18, type is buried.
-- synthesized logic cell
!_LC2_A18 = _LC2_A18~NOT;
_LC2_A18~NOT = LCELL(!clr);
-- Node name is ':20' = 'cnt00'
-- Equation name is 'cnt00', location is LC3_A18, type is buried.
cnt00 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ002 = cnt00 & !en
# !cnt00 & en;
-- Node name is ':19' = 'cnt01'
-- Equation name is 'cnt01', location is LC6_A18, type is buried.
cnt01 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ003 = !cnt00 & cnt01 & !_LC7_A18
# cnt00 & !cnt01 & en & !_LC7_A18
# cnt01 & !en;
-- Node name is ':18' = 'cnt02'
-- Equation name is 'cnt02', location is LC4_A18, type is buried.
cnt02 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ004 = cnt02 & !_LC5_A18 & !_LC7_A18
# !cnt02 & en & _LC5_A18 & !_LC7_A18
# cnt02 & !en;
-- Node name is ':17' = 'cnt03'
-- Equation name is 'cnt03', location is LC1_A18, type is buried.
cnt03 = DFFE( _EQ005, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ005 = !cnt02 & cnt03
# cnt03 & !_LC5_A18
# cnt02 & !cnt03 & en & _LC5_A18
# cnt03 & !en;
-- Node name is ':144' = 'cnt10'
-- Equation name is 'cnt10', location is LC1_A20, type is buried.
cnt10 = DFFE( _EQ006, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ006 = cin & !cnt10 & !_LC3_A20
# !cin & cnt10;
-- Node name is ':143' = 'cnt11'
-- Equation name is 'cnt11', location is LC2_A20, type is buried.
cnt11 = DFFE( _EQ007, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ007 = !cnt10 & cnt11 & !_LC3_A20
# cin & cnt10 & !cnt11 & !_LC3_A20
# !cin & cnt11;
-- Node name is ':142' = 'cnt12'
-- Equation name is 'cnt12', location is LC5_A20, type is buried.
cnt12 = DFFE( _EQ008, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ008 = cnt12 & !_LC3_A20 & !_LC4_A20
# cin & !cnt12 & !_LC3_A20 & _LC4_A20
# !cin & cnt12;
-- Node name is ':141' = 'cnt13'
-- Equation name is 'cnt13', location is LC8_A20, type is buried.
cnt13 = DFFE( _EQ009, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ009 = cin & !_LC3_A20 & _LC6_A20
# !cin & cnt13;
-- Node name is 'cout'
-- Equation name is 'cout', type is output
cout = _LC7_A20;
-- Node name is 'one0'
-- Equation name is 'one0', type is output
one0 = cnt00;
-- Node name is 'one1'
-- Equation name is 'one1', type is output
one1 = cnt01;
-- Node name is 'one2'
-- Equation name is 'one2', type is output
one2 = cnt02;
-- Node name is 'one3'
-- Equation name is 'one3', type is output
one3 = cnt03;
-- Node name is 'ten0'
-- Equation name is 'ten0', type is output
ten0 = cnt10;
-- Node name is 'ten1'
-- Equation name is 'ten1', type is output
ten1 = cnt11;
-- Node name is 'ten2'
-- Equation name is 'ten2', type is output
ten2 = cnt12;
-- Node name is 'ten3'
-- Equation name is 'ten3', type is output
ten3 = cnt13;
-- Node name is '|LPM_ADD_SUB:47|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A18', type is buried
_LC5_A18 = LCELL( _EQ010);
_EQ010 = cnt00 & cnt01;
-- Node name is '|LPM_ADD_SUB:171|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A20', type is buried
_LC4_A20 = LCELL( _EQ011);
_EQ011 = cnt10 & cnt11;
-- Node name is '|LPM_ADD_SUB:171|addcore:adder|:69' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC6_A20', type is buried
_LC6_A20 = LCELL( _EQ012);
_EQ012 = !cnt11 & cnt13
# !cnt10 & cnt13
# !cnt12 & cnt13
# cnt10 & cnt11 & cnt12 & !cnt13;
-- Node name is ':1'
-- Equation name is '_LC7_A20', type is buried
_LC7_A20 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, !_LC2_A18);
_EQ013 = cin & _LC3_A20
# !cin & _LC7_A20;
-- Node name is ':36'
-- Equation name is '_LC7_A18', type is buried
_LC7_A18 = LCELL( _EQ014);
_EQ014 = !cnt02 & !cnt03 & _LC5_A18;
-- Node name is ':160'
-- Equation name is '_LC3_A20', type is buried
!_LC3_A20 = _LC3_A20~NOT;
_LC3_A20~NOT = LCELL( _EQ015);
_EQ015 = cnt13
# cnt12
# !cnt11
# cnt10;
Project Information f:\clock\count24.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 24,810K
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