📄 testbed.v
字号:
/////////////////////////////////////////////////////////////// ICLAB Lab01 February, 2008// Exercise : Despreader gate-level design// Author : Chien-Ying Yu// Filename : TESTBED.v/////////////////////////////////////////////////////////////`timescale 1ns/10ps`include "PATTERN.v"`include "DESPREAD.v"module TESTBED;// wire declarationwire [3:0] A,B,C,D,E,F,G,H,I,J,K;wire [7:0] OUT;// module instantiationPATTERN DESPREAD_PATTERN( .OUT(OUT), .A(A), .B(B), .C(C), .D(D), .E(E), .F(F), .G(G), .H(H), .I(I), .J(J), .K(K));DESPREAD DESPREAD_DESIGN( .OUT(OUT), .A(A), .B(B), .C(C), .D(D), .E(E), .F(F), .G(G), .H(H), .I(I), .J(J), .K(K)); endmodule
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -