testbed.v

来自「Top module name : SHIFTER (File name : S」· Verilog 代码 · 共 32 行

///////////////////////////////////////////////////////////
//
// ICLAB Lab01 February, 2008
// Exercise    : Despreader gate-level design
// Author      : Chien-Ying Yu
// Filename    : TESTBED.v
//
///////////////////////////////////////////////////////////

`timescale 1ns/10ps

`include "PATTERN.v"
`include "DESPREAD.v"

module TESTBED;

// wire declaration
wire [3:0] A,B,C,D,E,F,G,H,I,J,K;
wire [7:0] OUT;

// module instantiation
PATTERN DESPREAD_PATTERN( .OUT(OUT), 
                          .A(A), .B(B), .C(C), .D(D),
                          .E(E), .F(F), .G(G), .H(H), 
                          .I(I), .J(J), .K(K));
DESPREAD DESPREAD_DESIGN( .OUT(OUT),
                          .A(A), .B(B), .C(C), .D(D),
                          .E(E), .F(F), .G(G), .H(H), 
                          .I(I), .J(J), .K(K));
                          
endmodule