pattern.v

来自「Top module name : SHIFTER (File name : S」· Verilog 代码 · 共 81 行

///////////////////////////////////////////////////////////
//
// ICLAB Lab01 February, 2008
// Exercise    : Despreader gate-level design
// Author      : Chien-Ying Yu
// Filename    : PATTERN.v
//
///////////////////////////////////////////////////////////

module PATTERN( A,B,C,D,E,F,G,H,I,J,K, OUT);

// input and output port declaration
output [3:0] A,B,C,D,E,F,G,H,I,J,K;
input [7:0] OUT;

// parameter declaration
parameter Seednum = 10;

// wire and register declaration
wire [7:0] C_OUT;
reg CLK;
reg [3:0] A,B,C,D,E,F,G,H,I,J,K;

// variable declaration
integer SEED;
real CYCLE;

// correct answer
assign C_OUT = {{4{A[3]}},A} - {{4{B[3]}},B} + {{4{C[3]}},C}
             + {{4{D[3]}},D} - {{4{E[3]}},E} + {{4{F[3]}},F}
             + {{4{G[3]}},G} + {{4{H[3]}},H} - {{4{I[3]}},I}
             - {{4{J[3]}},J} - {{4{K[3]}},K};

always #(CYCLE/2.0) CLK = ~CLK;

initial
begin
    $fsdbDumpfile("DESPREAD.fsdb");
    $fsdbDumpvars;
    CYCLE = 30.0;
    CLK = 1'b0;
    SEED = Seednum;
    for (CYCLE = 30.0; CYCLE > 9.9; CYCLE = CYCLE-0.1)
    begin
        // random testing

        repeat(100)
        begin
            @ (posedge CLK);
            A = $random(SEED);
            B = $random(SEED);
            C = $random(SEED);
            D = $random(SEED);
            E = $random(SEED);
            F = $random(SEED);
            G = $random(SEED);
            H = $random(SEED);
            I = $random(SEED);
            J = $random(SEED);
            K = $random(SEED);

            @ (posedge CLK);
            if (OUT !== C_OUT)
            begin
                $display("IN = %b,%b,%b,%b,%b,%b,%b,%b,%b,%b,%b",
                         A,B,C,D,E,F,G,H,I,J,K);
                $display("Your OUT = %b",OUT);
                $display("Correct OUT = %b",C_OUT);
                $display("Testing failed at CYCLE = %f",CYCLE);
                $finish;
            end
        end
       
        $display("Testing succeeded at CYCLE = %f",CYCLE);
    end
    
    $finish;
end

endmodule