simple.fit.summary

使用verilog语言控制CPLD通过红外收发器进行红外通讯

Fitter Status : Successful - Mon Sep 01 16:11:58 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : simple
Top-level Entity Name : simple
Family : MAX II
Device : EPM1270T144C5
Timing Models : Final
Total logic elements : 20 / 1,270 ( 2 % )
Total pins : 4 / 116 ( 3 % )
Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % )