frediv.v

我们的课程设计,三层电梯控制器模拟程序.用verilog HDL语言编写

module frediv(clki,clko);
	input clki;
	output clko;
	
	reg clko;
	
	parameter N = 10000;
	parameter WIDTH = 16;
	
	reg [WIDTH - 1:0] counter;
	always @(posedge clki)begin
		if(counter == N / 2 - 1)begin
			counter <= 0;
			clko <= ~clko;
		end else
			counter <= counter + 1;
	end
endmodule