dianti.v

我们的课程设计,三层电梯控制器模拟程序.用verilog HDL语言编写

module dianti(clk,rst,

				up_rq_1,
				up_rq_2,
				down_rq_2,
				down_rq_3,
				to_rq_1,
				to_rq_2,
				to_rq_3,
				
				up_rq_1_done,
				up_rq_2_done,
				down_rq_2_done,
				down_rq_3_done,
				to_rq_1_done,
				to_rq_2_done,
				to_rq_3_done,
				
				state_up,
				state_down,
				state_open,
				state_floor
				);
			
	input 			clk,rst;
	input			up_rq_1;
	input			up_rq_2;
	input			down_rq_2;
	input			down_rq_3;
	input			to_rq_1;
	input			to_rq_2;
	input			to_rq_3;
	
	output 			up_rq_1_done;
	output			up_rq_2_done;
	output			down_rq_2_done;
	output			down_rq_3_done;
	output			to_rq_1_done;
	output			to_rq_2_done;
	output			to_rq_3_done;
	
	output		    state_up;
	output			state_down;
	output			state_open;
	output	[1:0]	state_floor;
	
	reg 		up_rq_1_done;
	reg			up_rq_2_done;
	reg			down_rq_2_done;
	reg			down_rq_3_done;
	reg			to_rq_1_done;
	reg			to_rq_2_done;
	reg			to_rq_3_done;

	reg [4:0]   state;
	assign		state_up 		= state[0];
	assign		state_down 		= state[1];
	assign		state_open 		= state[2];
	assign		state_floor[1:0] = state[4:3];
	assign		clr_delay_counter = state[2];
	
	parameter	DELAY_COUNTER_N 		= 4;
	parameter	DELAY_COUNTER_WIDTH 	= 3;
	reg			[DELAY_COUNTER_WIDTH - 1 : 0]	delay_counter;
	wire								clr_delay_counter;
	
								
	parameter 	FLOOR1_OPEN 	= 5'b00_1_0_0,//FLOOR_OPEN_DOWN_UP
				FLOOR1_OPEN_UP 	= 5'b00_1_0_1,
				FLOOR1_CLOSE_UP = 5'b00_0_0_1,
				FLOOR1_STAND 	= 5'b00_0_0_0,
				
				FLOOR2_OPEN		= 5'b01_1_0_0,
				FLOOR2_OPEN_UP	= 5'b01_1_0_1,
				FLOOR2_OPEN_DOWN = 5'b01_1_1_0,
				FLOOR2_UP		= 5'b01_0_0_1,
				FLOOR2_DOWN		= 5'b01_0_1_0,
				FLOOR2_STAND	= 5'b01_0_0_0,
				
				FLOOR3_OPEN		= 5'b10_1_0_0,
				FLOOR3_OPEN_DOWN= 5'b10_1_1_0,
				FLOOR3_DOWN		= 5'b10_0_1_0,
				FLOOR3_STAND	= 5'b10_0_0_0;
	
				
	always @(posedge clk or negedge rst) begin
		if(~rst) begin
			state <= FLOOR1_OPEN;
			up_rq_1_done <= 1'b0;
			up_rq_2_done <= 1'b0;
			down_rq_2_done <= 1'b0;
			down_rq_3_done <= 1'b0;
			to_rq_1_done <= 1'b1;
			to_rq_2_done <= 1'b0;
			to_rq_3_done <= 1'b0;
			
		end else begin
			case(state)
			FLOOR1_OPEN: begin
					state <= FLOOR1_OPEN;
					//查询高层请求
					if(up_rq_2 | down_rq_2 | down_rq_3 | to_rq_2 | to_rq_3) begin//有请求
						state <= FLOOR1_OPEN_UP;
					end else if(delay_counter > DELAY_COUNTER_N) begin//时间到
						state <= FLOOR1_STAND;
					end
					
					up_rq_1_done <= 1'b0;
					up_rq_2_done <= 1'b0;
					down_rq_2_done <= 1'b0;
					down_rq_3_done <= 1'b0;
					to_rq_1_done <= 1'b1;
					to_rq_2_done <= 1'b0;
					to_rq_3_done <= 1'b0;
				end
			FLOOR1_STAND:begin
					state <= FLOOR1_STAND;
					//查询本层请求
					if(up_rq_1)begin
						state <= FLOOR1_OPEN_UP;
					end else if(to_rq_1 & (up_rq_2 | down_rq_2 | down_rq_3 | to_rq_2 | to_rq_3))begin
						state <= FLOOR1_OPEN_UP;
					end else if(to_rq_1)begin
						state <= FLOOR1_OPEN;
					//查询高层请求
					end else if(up_rq_2 | down_rq_2 | down_rq_3 | to_rq_2 | to_rq_3) begin
						state <= FLOOR2_UP;
					end
					up_rq_1_done <= 1'b0;
					up_rq_2_done <= 1'b0;
					down_rq_2_done <= 1'b0;
					down_rq_3_done <= 1'b0;
					to_rq_1_done <= 1'b0;
					to_rq_2_done <= 1'b0;
					to_rq_3_done <= 1'b0;
				end
			FLOOR1_OPEN_UP:begin
					state <= FLOOR1_OPEN_UP;
					if(delay_counter > DELAY_COUNTER_N) begin //时间到
						//查询高层请求
						if(up_rq_2 | down_rq_2 | down_rq_3 | to_rq_2 | to_rq_3)begin
							state <= FLOOR1_CLOSE_UP;
						end else begin//无高层请求
							state <= FLOOR1_STAND;
						end
					end
					
					up_rq_1_done <= 1'b1;
					up_rq_2_done <= 1'b0;
					down_rq_2_done <= 1'b0;
					down_rq_3_done <= 1'b0;
					to_rq_1_done <= 1'b1;
					to_rq_2_done <= 1'b0;
					to_rq_3_done <= 1'b0;
				end
			FLOOR1_CLOSE_UP:begin
					state <= FLOOR2_UP;
					
					up_rq_1_done <= 1'b0;
					up_rq_2_done <= 1'b0;
					down_rq_2_done <= 1'b0;
					down_rq_3_done <= 1'b0;
					to_rq_1_done <= 1'b0;
					to_rq_2_done <= 1'b0;
					to_rq_3_done <= 1'b0;
				end
			FLOOR2_OPEN:begin
					state <= FLOOR2_OPEN;
					//查询高层请求
					if(down_rq_3 | to_rq_3 | up_rq_2)begin
						state <= FLOOR2_OPEN_UP;
					//查询下层请求
					end else if(up_rq_1 | to_rq_1 | down_rq_2) begin
						state <= FLOOR2_OPEN_DOWN;
					//时间到
					end else if(delay_counter > DELAY_COUNTER_N) begin
						state <= FLOOR2_STAND;
					end
					
					up_rq_1_done <= 1'b0;
					up_rq_2_done <= 1'b0;
					down_rq_2_done <= 1'b0;
					down_rq_3_done <= 1'b0;
					to_rq_1_done <= 1'b0;
					to_rq_2_done <= 1'b1;
					to_rq_3_done <= 1'b0;
				end
			FLOOR2_OPEN_UP:begin
					state <= FLOOR2_OPEN_UP;
					//时间到
					if(delay_counter > DELAY_COUNTER_N) begin
						if(down_rq_3 | to_rq_3 )begin
							state <= FLOOR2_UP;
						end else if(up_rq_1 | to_rq_1 | down_rq_2) begin
							state <= FLOOR2_OPEN_DOWN;
						end else begin
							state <= FLOOR2_STAND;
						end
					end 
					up_rq_1_done <= 1'b0;
					up_rq_2_done <= 1'b1;
					down_rq_2_done <= 1'b0;
					down_rq_3_done <= 1'b0;
					to_rq_1_done <= 1'b0;
					to_rq_2_done <= 1'b1;
					to_rq_3_done <= 1'b0;
				end
			FLOOR2_OPEN_DOWN:begin
					state <= FLOOR2_OPEN_DOWN;
					//时间到
					if(delay_counter > DELAY_COUNTER_N)begin
						if(up_rq_1 | to_rq_1) begin
							state <= FLOOR2_DOWN;
						end else if(down_rq_3 | to_rq_3 | up_rq_2)begin
							state <= FLOOR2_OPEN_UP;
						end else begin
							state <= FLOOR2_STAND;
						end
					end
					up_rq_1_done <= 1'b0;
					up_rq_2_done <= 1'b0;
					down_rq_2_done <= 1'b1;
					down_rq_3_done <= 1'b0;
					to_rq_1_done <= 1'b0;
					to_rq_2_done <= 1'b1;
					to_rq_3_done <= 1'b0;
				end
			FLOOR2_UP:begin
					state <= FLOOR3_STAND;
					//查询本层请求
					if(up_rq_2)begin
						state <= FLOOR2_OPEN_UP;
					end else if(to_rq_2)begin
						state <= FLOOR2_OPEN;
						if(to_rq_3 | down_rq_3)
							state <= FLOOR2_OPEN_UP;
						else if(to_rq_1 | up_rq_1)
							state <= FLOOR2_OPEN_DOWN;
					end else if(to_rq_3 | down_rq_3)begin
						state <= FLOOR3_STAND;
					end else begin
						state <= FLOOR2_OPEN_DOWN;
					end 
					up_rq_1_done <= 1'b0;
					up_rq_2_done <= 1'b0;
					down_rq_2_done <= 1'b0;
					down_rq_3_done <= 1'b0;
					to_rq_1_done <= 1'b0;
					to_rq_2_done <= 1'b0;
					to_rq_3_done <= 1'b0;
				end
			FLOOR2_DOWN:begin
					if(down_rq_2)begin
						state <= FLOOR2_OPEN_DOWN;
					end else if(to_rq_2)begin
						state <= FLOOR2_OPEN;
						if(to_rq_1 | up_rq_1)begin
							state <= FLOOR2_OPEN_DOWN;
						end else if(to_rq_3 | down_rq_3) begin
							state <= FLOOR2_OPEN_UP;
						end
					end else if(to_rq_1 | up_rq_1)begin
						state <= FLOOR1_STAND;
					end else begin
						state <= FLOOR2_OPEN_UP;
					end
					up_rq_1_done <= 1'b0;
					up_rq_2_done <= 1'b0;
					down_rq_2_done <= 1'b0;
					down_rq_3_done <= 1'b0;
					to_rq_1_done <= 1'b0;
					to_rq_2_done <= 1'b0;
					to_rq_3_done <= 1'b0;
				end
			FLOOR2_STAND:begin
					state <= FLOOR2_STAND;
					if(to_rq_2)
						state <= FLOOR2_OPEN;
					else if(up_rq_2)
						state <= FLOOR2_OPEN_UP;
					else if(down_rq_2)
						state <= FLOOR2_OPEN_DOWN;
					else if(to_rq_3 | down_rq_3)
						state <= FLOOR3_STAND;
					else if(to_rq_1 | up_rq_1)
						state <= FLOOR1_STAND;
					up_rq_1_done <= 1'b0;
					up_rq_2_done <= 1'b0;
					down_rq_2_done <= 1'b0;
					down_rq_3_done <= 1'b0;
					to_rq_1_done <= 1'b0;
					to_rq_2_done <= 1'b0;
					to_rq_3_done <= 1'b0;
				end
				
			FLOOR3_OPEN:begin
					state <= FLOOR3_OPEN;
					//查询下层请求
					if(up_rq_1 | up_rq_2 | to_rq_1 | to_rq_2 | down_rq_3 | down_rq_2) begin
						state <= FLOOR3_OPEN_DOWN;
					//时间到
					end else if(delay_counter > DELAY_COUNTER_N) begin
						state <= FLOOR3_STAND;
					end
					up_rq_1_done <= 1'b0;
					up_rq_2_done <= 1'b0;
					down_rq_2_done <= 1'b0;
					down_rq_3_done <= 1'b0;
					to_rq_1_done <= 1'b0;
					to_rq_2_done <= 1'b0;
					to_rq_3_done <= 1'b1;
				end
			FLOOR3_OPEN_DOWN:begin
					state <= FLOOR3_OPEN_DOWN;
					if(delay_counter > DELAY_COUNTER_N) begin
						if(up_rq_1 | up_rq_2 | to_rq_1 | to_rq_2 | down_rq_2)begin
							state <= FLOOR3_DOWN;
						end else begin
							state <= FLOOR3_STAND;
						end
					end
					up_rq_1_done <= 1'b0;
					up_rq_2_done <= 1'b0;
					down_rq_2_done <= 1'b0;
					down_rq_3_done <= 1'b1;
					to_rq_1_done <= 1'b0;
					to_rq_2_done <= 1'b0;
					to_rq_3_done <= 1'b1;
				end
				
			FLOOR3_DOWN:begin
					state <= FLOOR2_DOWN;
					up_rq_1_done <= 1'b0;
					up_rq_2_done <= 1'b0;
					down_rq_2_done <= 1'b0;
					down_rq_3_done <= 1'b0;
					to_rq_1_done <= 1'b0;
					to_rq_2_done <= 1'b0;
					to_rq_3_done <= 1'b0;
				end
			FLOOR3_STAND:begin
					state <= FLOOR3_STAND;
					if(to_rq_3)
						state <= FLOOR3_OPEN;
					else if(down_rq_3)
						state <= FLOOR3_OPEN_DOWN;
					else if(up_rq_1 | up_rq_2 | to_rq_1 | to_rq_2 | down_rq_2)
						state <= FLOOR2_DOWN;
					up_rq_1_done <= 1'b0;
					up_rq_2_done <= 1'b0;
					down_rq_2_done <= 1'b0;
					down_rq_3_done <= 1'b0;
					to_rq_1_done <= 1'b0;
					to_rq_2_done <= 1'b0;
					to_rq_3_done <= 1'b0;
				end
			default:begin
					state <= FLOOR1_OPEN;
					up_rq_1_done <= 1'b0;
					up_rq_2_done <= 1'b0;
					down_rq_2_done <= 1'b0;
					down_rq_3_done <= 1'b0;
					to_rq_1_done <= 1'b1;
					to_rq_2_done <= 1'b0;
					to_rq_3_done <= 1'b0;
				end
			endcase
		end
	end
	
	always @(posedge clk or negedge clr_delay_counter) begin
		if(~clr_delay_counter) begin
			delay_counter <= 0;
		end else begin
			delay_counter <= delay_counter + 1'b1;
		end
	end
endmodule