📄 ansy_fifo_top.v
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/************************************************* * 模块名:asyn_fifo_top * 时 间:2007-05-14 * 设计者:张波涛 * 说 明:FIFO的顶层模块 *************************************************/ // `include "timescale.v" module asyn_fifo_top( rdata, //FIFO读数据总线 wfull, //FIFO满信号 rempty, //FIFO空信号 wdata, //FIFO写数据总线 winc, //写请求信号 wclk, //写时钟 wrst_n, //写时钟域复位信号 rinc, //读请求信号 rclk, //读时钟 rrst_n //读时钟域复位信号 ); parameter DSIZE = 32; parameter ASIZE = 3; output [DSIZE - 1: 0] rdata; output wfull; output rempty; input [DSIZE -1:0] wdata; input winc,wclk,wrst_n; input rinc,rclk,rrst_n; wire [ASIZE -1:0] waddr,raddr; wire [ASIZE :0] wptr,rptr,wrptr2,rwptr2; sync_r2w #(ASIZE) sync_r2w (.wrptr2(wrptr2), .rptr(rptr), .wclk(wclk), .wrst_n(wrst_n)); sync_w2r #(ASIZE) sync_w2r (.rwptr2(rwptr2), .wptr(wptr), .rclk(rclk), .rrst_n(rrst_n)); fifomem #(DSIZE,ASIZE) fifomem( .rdata(rdata), .wdata(wdata), .waddr(waddr), .raddr(raddr), .wclken(winc), .wclk(wclk)); rptr_empty #(ASIZE) rptr_empty( .rempty(rempty), .raddr(raddr), .rptr(rptr), .rwptr2(rwptr2), .rinc(rinc), .rclk(rclk), .rrst_n(rrst_n)); wptr_full #(ASIZE) wptr_full( .wfull(wfull), .waddr(waddr), .wptr(wptr), .wrptr2(wrptr2), .winc(winc), .wclk(wclk), .wrst_n(wrst_n)); endmodule
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