genetricsynchronizer.v

多时钟域下同步逻辑的RTL代码（包括数据同步器和控制信号万能同步器）

//---------------------------------------------------------------------
// Author       : BrianChang
// ModuleName   : GenetricSynchronizer
// Created On   : 2008-02-24
// Description  : Synchronizer for all Clockes
// Copyright (c) 2008 by SDRGroup@627. This model is the confidential and
// proprietary property of SDRGroup and the possession or use of this
// file requires a written license from SDRGroup.
//----------------------------------------------------------------------

module GenetricSynchronizer
(
     GS_CLK1,
     GS_RST_N1,
     
     GS_CLK2,
     GS_RST_N2,
    
     GS_W_Req_CLK1,
     GS_W_ACK_CLK1,
     
     GS_W_Req_CLK2
       
);

//-----------------------------------Input&Output Part------------------------------------
input                    GS_CLK1;
input                    GS_CLK2;
                         
input                    GS_RST_N1;
input                    GS_RST_N2;

input                    GS_W_Req_CLK1;
output                   GS_W_ACK_CLK1;
output                   GS_W_Req_CLK2;

//--------------------------------------Req Synchronizer Part----------------------------
reg  rReqPluse2_CLK1;
reg  rReqPluse2_Syn1_CLK2;
reg  rReqPluse2_Syn2_CLK2;
reg  rReqPluse_CLK2;
reg  rGS_W_Req_CLK2;

always@(posedge GS_CLK1 or negedge GS_RST_N1)
begin
    if(~GS_RST_N1)
         rReqPluse2_CLK1 <= 1'd0;
    else 
         if(GS_W_Req_CLK1)
             rReqPluse2_CLK1 <=  ~rReqPluse2_CLK1;
         else
             rReqPluse2_CLK1 <= rReqPluse2_CLK1;  
end

always@(posedge GS_CLK2 or negedge GS_RST_N2)
begin
    if(~GS_RST_N2)
    begin
        rReqPluse2_Syn1_CLK2 <= 0;
        rReqPluse2_Syn2_CLK2 <= 0;        
    end
    else
    begin
        rReqPluse2_Syn2_CLK2 <= rReqPluse2_Syn1_CLK2;
        rReqPluse2_Syn1_CLK2 <= rReqPluse2_CLK1;
    end
end

always@(posedge GS_CLK2 or negedge GS_RST_N2)
begin
    if(~GS_RST_N2)
        rReqPluse_CLK2 <= 0;
    else
        rReqPluse_CLK2 <= rReqPluse2_Syn2_CLK2;
end

always@(posedge GS_CLK2 or negedge GS_RST_N2)
begin
    if(~GS_RST_N2)
        rGS_W_Req_CLK2 <= 0;
    else
        rGS_W_Req_CLK2 <= rReqPluse2_Syn2_CLK2 ^ rReqPluse_CLK2;    
end

assign GS_W_Req_CLK2 = rGS_W_Req_CLK2;

//--------------------------------------ACK Synchronizer Part-----------------------------
reg  rACKPluse2_CLK2;
reg  rACKPluse2_Syn1_CLK1;
reg  rACKPluse2_Syn2_CLK1;
reg  rACKPluse_CLK1;
reg  rGS_W_ACK_CLK1;

always@(posedge GS_CLK2 or negedge GS_RST_N2)
begin
    if(~GS_RST_N2)
          rACKPluse2_CLK2 <= 0;
    else
       if(rGS_W_Req_CLK2)   
          rACKPluse2_CLK2 <= ~rACKPluse2_CLK2;
       else
          rACKPluse2_CLK2 <= rACKPluse2_CLK2;   
end

always@(posedge GS_CLK1 or negedge GS_RST_N1)
begin
    if(~GS_RST_N1)
    begin
       rACKPluse2_Syn2_CLK1 <= 0;
       rACKPluse2_Syn1_CLK1 <= 0;       
    end
    else
    begin
       rACKPluse2_Syn2_CLK1 <= rACKPluse2_Syn1_CLK1;
       rACKPluse2_Syn1_CLK1 <= rACKPluse2_CLK2; 
    end   
end

always@(posedge GS_CLK1 or negedge GS_RST_N1)
begin
    if(~GS_RST_N1)
       rACKPluse_CLK1 <= 0;
    else 
       rACKPluse_CLK1 <=  rACKPluse2_Syn2_CLK1;  
end

always@(posedge GS_CLK1 or negedge GS_RST_N1)
begin
    if(~GS_RST_N1)
       rGS_W_ACK_CLK1 <= 0;
    else 
       rGS_W_ACK_CLK1 <=  rACKPluse_CLK1 ^ rACKPluse2_Syn2_CLK1;
end

assign GS_W_ACK_CLK1 = rGS_W_ACK_CLK1;

endmodule