viterbi_node_sync.vhd

一个完整的viterbi编码程序

-------------------------------------------------------------------------
-------------------------------------------------------------------------
--
-- Revision Control Information
--
-- Description	:  
--
-- Copyright 2003 (c) Altera Corporation
-- All rights reserved
--
-------------------------------------------------------------------------
-------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
library Viterbi;


ENTITY viterbi_node_sync IS
    GENERIC
	(
		BER_threshold_val : NATURAL := 30;
		BER_monitor_len : NATURAL := 100;
		monitor_len_max : NATURAL := 10;
		numerr_max : NATURAL := 14;
		NUMERR_SIZE : NATURAL := 14;
		softbits : NATURAL := 4;
		n_max : NATURAL := 2;
		rr_size : NATURAL := 8;
		log2_n_max : NATURAL := 1;
		constraint_length_m_1 : NATURAL := 6;
		vlog_wide : NATURAL := 6;
		bmgwide : NATURAL := 9
		
	);
	PORT (
		clk	: IN STD_LOGIC;
		reset	: IN STD_LOGIC;
		sink_dav_master	: IN STD_LOGIC;
		source_ena_slave	: IN STD_LOGIC;
		sink_val	: IN STD_LOGIC;
		sink_sop	: IN STD_LOGIC;
		sink_eop	: IN STD_LOGIC;
		rr	: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
		eras_sym	: IN STD_LOGIC_VECTOR (2 DOWNTO 1);
		tr_init_state	: IN STD_LOGIC_VECTOR (6 DOWNTO 1);
		tb_type	: IN STD_LOGIC;
		tb_length	: IN STD_LOGIC_VECTOR (6 DOWNTO 1);
		sink_ena_master	: OUT STD_LOGIC;
		source_dav_slave	: OUT STD_LOGIC;
		source_val	: OUT STD_LOGIC;
		source_sop	: OUT STD_LOGIC;
		source_eop	: OUT STD_LOGIC;
		decbit	: OUT STD_LOGIC;
		normalizations	: OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
		bestadd	: OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
		bestmet	: OUT STD_LOGIC_VECTOR (9 DOWNTO 1);
		numerr	: OUT STD_LOGIC_VECTOR (numerr_max DOWNTO 1);
		out_sync : OUT STD_LOGIC;
		node_state_sync : OUT STD_LOGIC_VECTOR (2 DOWNTO 1)
	);
END viterbi_node_sync;



ARCHITECTURE arch_viterbi_node_sync OF viterbi_node_sync IS


	SIGNAL out_sync_sig : STD_LOGIC;
	SIGNAL rr_in : STD_LOGIC_VECTOR (8 downto 1);
	SIGNAL rr_out : STD_LOGIC_VECTOR (8 downto 1);
	SIGNAL numerr_sig : STD_LOGIC_VECTOR (numerr_max downto 1);
	SIGNAL source_val_sig : STD_LOGIC;
	SIGNAL source_sop_sig : STD_LOGIC;
	SIGNAL source_eop_sig : STD_LOGIC;
	
	
	COMPONENT ber_node_sync 
	GENERIC
	(
		BER_threshold_val : NATURAL;
		BER_monitor_len : NATURAL;
		monitor_len_max : NATURAL;
		numerr_max : NATURAL;
		softbits : NATURAL;
		n_max : NATURAL
		
	);
	PORT
	(
		clk : in std_logic;
		reset : in std_logic;
		numerr : in std_logic_vector ( numerr_max downto 1);
		source_val : in std_logic;
		source_sop : in std_logic;
		source_eop : in std_logic;
       	out_sync : out std_logic;
		rr_in : in std_logic_vector(n_max * softbits downto 1);
      	rr_rotate: out std_logic_vector(n_max * softbits downto 1);
		node_state_sync : out std_logic_vector(n_max downto 1)
	);
	END COMPONENT;
	
	
	component viterbi_BER
    	port (
			clk : in Std_Logic;
			reset : in Std_Logic;
			sink_dav_master : in  Std_Logic; 
			sink_ena_master : out Std_Logic; 
			sink_val        : in  Std_Logic; 
			sink_sop        : in  Std_Logic; 
			sink_eop        : in  Std_Logic; 
			rr : in Std_Logic_Vector(rr_size downto 1);
			eras_sym : in Std_Logic_Vector(n_max downto 1);
  
			numerr : out Std_Logic_Vector(numerr_size downto 1);

			tr_init_state : in Std_Logic_Vector(constraint_length_m_1 downto 1);
			tb_type : in Std_Logic;
			tb_length     : in Std_Logic_Vector(vlog_wide downto 1);
			source_dav_slave : out Std_Logic; 
			source_ena_slave : in Std_Logic; 
			source_val : out Std_Logic; 
			source_sop : out Std_Logic; 
			source_eop : out Std_Logic; 
			decbit : out Std_Logic;
			bestmet : out Std_Logic_Vector(bmgwide downto 1);
			bestadd : out Std_Logic_Vector(constraint_length_m_1 downto 1);
			normalizations : out Std_Logic_Vector(8 downto 1)
	 		);
	end component;
	
	
BEGIN
		
	source_val <= source_val_sig;
	out_sync <= out_sync_sig;
	numerr <= numerr_sig;
	rr_in <= rr;
	source_sop <= source_sop_sig;
	source_eop <= source_eop_sig;
	
	
	ber_node_sync_inst : ber_node_sync
	GENERIC MAP (
		BER_threshold_val => BER_threshold_val,
		BER_monitor_len => BER_monitor_len,
		monitor_len_max => monitor_len_max,
		numerr_max => numerr_max,
		softbits => softbits,
		n_max => n_max
	)
	PORT MAP (
		clk  =>  clk,
		reset  =>  reset,
		numerr  =>  numerr_sig,
		source_val => source_val_sig,
		source_sop => source_sop_sig,
		source_eop => source_eop_sig,
		out_sync => out_sync_sig,
		rr_in => rr_in, 
      	rr_rotate => rr_out,
		node_state_sync => node_state_sync
	);
	
	viterbi_BER_inst : viterbi_BER
	PORT MAP(
		clk => clk, 
		reset => reset, 

		sink_dav_master => sink_dav_master, 
		sink_ena_master => sink_ena_master,
		sink_val => sink_val, 
		sink_sop => sink_sop, 
		sink_eop => sink_eop, 

		source_dav_slave => source_dav_slave,
		source_ena_slave => source_ena_slave,
		source_val => source_val_sig,
		source_sop => source_sop_sig,
		source_eop => source_eop_sig,

		
		tr_init_state => tr_init_state, 
		tb_type => tb_type, 
		tb_length => tb_length, 

 		rr => rr_out, 
		numerr => numerr_sig,
		normalizations => normalizations, 
		bestadd => bestadd,
		bestmet => bestmet, 
 		decbit => decbit, 
 		eras_sym => eras_sym
 		);

	

END arch_viterbi_node_sync;