📄 viterbi_ber.html
字号:
<HTML><HEAD><style>
A.h:hover { color: "#FF0000"; }A.menu:link { text-decoration: none}A.menu:visited{ text-decoration: none}A.menu:hover {color: #EE9B06;}A.submenu:link { text-decoration: none;}A.submenu:visited { text-decoration: none}A.submenu:hover {color: #EE9B06;}div.category { border-bottom: 5px, solid, black; }br.submenu { line-height: 1em;}br.submenu { line-height: 7px;}BODY, H1, H2, H3, H4, TD, TH, UL, OL, LI, P, DD, DT, DL, INPUT, SELECT, SPAN { font-family : SansSerif, Verdana, Helvetica, Arial, San-sarif; }BODY { background-color : #e0e0e0; }TD, UL, OL, LI, P, DD, DT, DL, SPAN { font-size: 11pt; color : black; }BLOCKQUOTE { font-size: 10pt; color : #000099; }TH { font-size : 11pt; font-weight : bold; font-style : normal; color : black; }H1 { font-size : 18pt; color : black; }H2 { font-size : 14pt; color : black; }H3 { font-size : 12pt; color : black; }H4 { font-size : 11pt; font-weight : bold; color : black; }
</style></HEAD><BODY align=left style='background-color: #ffffff;'><DIV align=left><TABLE width=95% border=0 cellpadding=2><TR><TD><TABLE cellpadding=2 border=0 ><TR><WIZARD></WIZARD><TD><H1>Generation Report - Viterbi Compiler v4.1.0</H1></TD></TR></TABLE></TD></TR><TR><TD><TABLE cellpadding=2 border=1 width=60%><TR><TD><B>Entity Name</B></TD><TD>auk_vit_par_top_atl</TD></TR><TR><TD><B>Variation Name</B></TD><TD>viterbi_BER</TD></TR><TR><TD><B>Variation HDL</B></TD><TD>VHDL</TD></TR><TR><TD><B>Output Directory</B></TD><TD>C:\altera\design_examples\viterbi_node_sync\source</TD></TR></TABLE></TD></TR><TR><TD><h2>File Summary</h2>IP Toolbench is creating the following files in the output directory:</TD></TR><TR><TD><TABLE cellspacing=2 cellpadding=2 border=1 width=100%><TR align=left><TH align=left align=top width=25%><B>File</B></TH><TH align=left><B>Description</B></TH></TR><TR><TD>viterbi_BER.vhd</TD><TD>A MegaCore<small><sup>®</sup></small> function variation file, which defines a VHDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.</TD></TR><TR><TD>viterbi_BER_inst.vhd</TD><TD>VHDL sample instantiation file</TD></TR><TR><TD>viterbi_BER.cmp</TD><TD>A VHDL component declaration for the MegaCore function variation. Add the contents of this file to any VHDL architecture that instantiates the MegaCore function.</TD></TR><TR><TD>viterbi_BER.inc</TD><TD>An AHDL include declaration file for the MegaCore function variation. Include this file with any AHDL architecture that instantiates the MegaCore function.</TD></TR><TR><TD>viterbi_BER_bb.v</TD><TD>Verilog HDL black-box file for the MegaCore function variation. Use this file when using a third-party EDA tool to synthesize your design.</TD></TR><TR><TD>viterbi_BER.bsf</TD><TD>Quartus<small><sup>®</sup></small> II symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor.</TD></TR><TR><TD>viterbi_BER.vho</TD><TD>VHDL IP functional simulation model.</TD></TR><TR><TD>viterbi_BER.html</TD><TD>The MegaCore function report file.</TD></TR></TABLE></TD></TR><TR><TD><h2>MegaCore Function Variation File Parameters</h2><TABLE border=1 cellpadding=2 cellspacing=0 width=75%><TR align=left><TH align=left><B>Name</B></TH><TH align=left><B>Value</B></TH></TR><TR ><TD>N</TD><TD>2</TD></TR><TR ><TD>L</TD><TD>7</TD></TR><TR ><TD>DEC_MODE</TD><TD>V</TD></TR><TR ><TD>NCODES</TD><TD>1</TD></TR><TR ><TD>N_MAX</TD><TD>2</TD></TR><TR ><TD>LOG2_N_MAX</TD><TD>1</TD></TR><TR ><TD>RR_SIZE</TD><TD>8</TD></TR><TR ><TD>CONSTRAINT_LENGTH_M_1</TD><TD>6</TD></TR><TR ><TD>V</TD><TD>42</TD></TR><TR ><TD>SOFTBITS</TD><TD>4</TD></TR><TR ><TD>BMGWIDE</TD><TD>9</TD></TR><TR ><TD>VLOG_WIDE</TD><TD>6</TD></TR><TR ><TD>SEL_CODE_SIZE</TD><TD>1</TD></TR><TR ><TD>ga</TD><TD>91</TD></TR><TR ><TD>gb</TD><TD>121</TD></TR><TR ><TD>gc</TD><TD>23</TD></TR><TR ><TD>gd</TD><TD>0</TD></TR><TR ><TD>ge</TD><TD>0</TD></TR><TR ><TD>gf</TD><TD>0</TD></TR><TR ><TD>gg</TD><TD>0</TD></TR><TR ><TD>BER</TD><TD>used</TD></TR><TR ><TD>CONF_MODE</TD><TD>Atlantic</TD></TR><TR ><TD>NODE_SYNC</TD><TD>unused</TD></TR><TR ><TD>FAMILY</TD><TD>Stratix</TD></TR><TR ><TD>NUMERR_SIZE</TD><TD>14</TD></TR></TABLE></TD></TR><TR><TD><h2>MegaCore Function Variation File Ports</h2><TABLE border=1 cellpadding=2 cellspacing=0 width=75%><TR align=left><TH align=left><B>Name</B></TH><TH align=left><B>Direction</B></TH><TH align=left><B>Width</B></TH></TR><TR><TD>clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>reset</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>sink_dav_master</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>source_ena_slave</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>sink_val</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>sink_sop</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>sink_eop</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>rr</TD><TD>INPUT</TD><TD>8</TD></TR><TR><TD>eras_sym</TD><TD>INPUT</TD><TD>2</TD></TR><TR><TD>state_node_sync</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>sel_code</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>tr_init_state</TD><TD>INPUT</TD><TD>6</TD></TR><TR><TD>tb_type</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>tb_length</TD><TD>INPUT</TD><TD>6</TD></TR><TR><TD>sink_ena_master</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>source_dav_slave</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>source_val</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>source_sop</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>source_eop</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>decbit</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>normalizations</TD><TD>OUTPUT</TD><TD>8</TD></TR><TR><TD>bestadd</TD><TD>OUTPUT</TD><TD>6</TD></TR><TR><TD>bestmet</TD><TD>OUTPUT</TD><TD>9</TD></TR><TR><TD>numerr</TD><TD>OUTPUT</TD><TD>14</TD></TR></TABLE></TD></TR></TD></TR></TABLE></DIV></BODY></HTML>⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -