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ERROR:HDLCompilers:26 - "212bianmaqi.v" line 60 expecting 'endmodule', found 'end'Analysis of file <"bianma.prj"> failed.--> Total memory usage is 76776 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledERROR:HDLCompilers:26 - "212bianmaqi.v" line 60 expecting 'endmodule', found 'end'Analysis of file <"bianma.prj"> failed.--> Total memory usage is 76776 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledERROR:HDLCompilers:120 - "212bianmaqi.v" line 38 Illegal redeclaration of input 'Din' as a regModule <bianma> compiledERROR:HDLCompilers:26 - "212bianmaqi.v" line 60 expecting 'endmodule', found 'end'Analysis of file <"bianma.prj"> failed.--> Total memory usage is 76776 kilobytesNumber of errors : 2 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledERROR:HDLCompilers:26 - "212bianmaqi.v" line 60 expecting 'endmodule', found 'end'Analysis of file <"bianma.prj"> failed.--> Total memory usage is 76776 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledERROR:HDLCompilers:26 - "212bianmaqi.v" line 54 expecting 'endmodule', found 'if'Analysis of file <"bianma.prj"> failed.--> Total memory usage is 76776 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledERROR:HDLCompilers:26 - "212bianmaqi.v" line 50 expecting 'endmodule', found 'if'Analysis of file <"bianma.prj"> failed.--> Total memory usage is 76776 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledERROR:HDLCompilers:26 - "212bianmaqi.v" line 54 expecting 'endmodule', found 'if'Analysis of file <"bianma.prj"> failed.--> Total memory usage is 76776 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledERROR:HDLCompilers:26 - "212bianmaqi.v" line 54 expecting 'endmodule', found 'if'Analysis of file <"bianma.prj"> failed.--> Total memory usage is 76776 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledERROR:HDLCompilers:247 - "212bianmaqi.v" line 51 Reference to scalar wire 'Dout1' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "212bianmaqi.v" line 51 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - "212bianmaqi.v" line 52 Reference to scalar wire 'Dout2' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "212bianmaqi.v" line 52 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - "212bianmaqi.v" line 56 Reference to scalar wire 'Dout' is not a legal reg or variable lvalueERROR:HDLCompilers:42 - "212bianmaqi.v" line 56 Illegal left hand side of procedural assignERROR:HDLCompilers:247 - "212bianmaqi.v" line 60 Reference to scalar wire 'Dout' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "212bianmaqi.v" line 60 Illegal left hand side of blocking assignmentAnalysis of file <"bianma.prj"> failed.--> Total memory usage is 76776 kilobytesNumber of errors : 8 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledERROR:HDLCompilers:247 - "212bianmaqi.v" line 51 Reference to scalar wire 'Dout1' is not a legal reg or variable lvalueERROR:HDLCompilers:42 - "212bianmaqi.v" line 51 Illegal left hand side of procedural assignERROR:HDLCompilers:247 - "212bianmaqi.v" line 52 Reference to scalar wire 'Dout2' is not a legal reg or variable lvalueERROR:HDLCompilers:42 - "212bianmaqi.v" line 52 Illegal left hand side of procedural assignERROR:HDLCompilers:247 - "212bianmaqi.v" line 56 Reference to scalar wire 'Dout' is not a legal reg or variable lvalueERROR:HDLCompilers:42 - "212bianmaqi.v" line 56 Illegal left hand side of procedural assignERROR:HDLCompilers:247 - "212bianmaqi.v" line 60 Reference to scalar wire 'Dout' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "212bianmaqi.v" line 60 Illegal left hand side of blocking assignmentAnalysis of file <"bianma.prj"> failed.--> Total memory usage is 76776 kilobytesNumber of errors : 8 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledERROR:HDLCompilers:247 - "212bianmaqi.v" line 51 Reference to scalar wire 'Dout1' is not a legal reg or variable lvalueERROR:HDLCompilers:42 - "212bianmaqi.v" line 51 Illegal left hand side of procedural assignERROR:HDLCompilers:247 - "212bianmaqi.v" line 52 Reference to scalar wire 'Dout2' is not a legal reg or variable lvalueERROR:HDLCompilers:42 - "212bianmaqi.v" line 52 Illegal left hand side of procedural assignERROR:HDLCompilers:247 - "212bianmaqi.v" line 55 Reference to scalar wire 'Dout' is not a legal reg or variable lvalueERROR:HDLCompilers:42 - "212bianmaqi.v" line 55 Illegal left hand side of procedural assignERROR:HDLCompilers:247 - "212bianmaqi.v" line 57 Reference to scalar wire 'Dout' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "212bianmaqi.v" line 57 Illegal left hand side of blocking assignmentAnalysis of file <"bianma.prj"> failed.--> Total memory usage is 76776 kilobytesNumber of errors : 8 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledNo errors in compilationAnalysis of file <"bianma.prj"> succeeded. =========================================================================* HDL Analysis *=========================================================================ERROR:HDLCompilers:246 - "212bianmaqi.v" line 42 Reference to scalar reg 'D1' is not a legal net lvalueERROR:HDLCompilers:102 - "212bianmaqi.v" line 42 Connection to output port 'Q' must be a net lvalueERROR:HDLCompilers:246 - "212bianmaqi.v" line 47 Reference to scalar reg 'D2' is not a legal net lvalueERROR:HDLCompilers:102 - "212bianmaqi.v" line 47 Connection to output port 'Q' must be a net lvalue--> Total memory usage is 76776 kilobytesNumber of errors : 4 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "View RTL Schematic" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "212bianmaqi.v"Module <DFF> compiledModule <bianma> compiledNo errors in compilationAnalysis of file <"bianma.prj"> succeeded. ⌨️ 快捷键说明
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