bianma.syr

一个完整的viterbi(2,1,7)编码程序

Release 7.1i - xst H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--> Reading design: bianma.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "bianma.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "bianma"
Output Format                      : NGC
Target Device                      : acr2

---- Source Options
Top Module Name                    : bianma
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : YES
RTL Output                         : ONLY
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain

---- Other Options
lso                                : bianma.lso
verilog2001                        : YES
safe_implementation                : No
Clock Enable                       : YES
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "212bianmaqi.v"
Module <DFF> compiled
Module <BC> compiled
Module <bianma> compiled
No errors in compilation
Analysis of file <"bianma.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <bianma>.
Module <bianma> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <bianma>.
Analyzing module <DFF>.
Module <DFF> is correct for synthesis.
 
Analyzing module <BC>.
Module <BC> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <BC>.
    Related source file is "212bianmaqi.v".
Unit <BC> synthesized.


Synthesizing Unit <DFF>.
    Related source file is "212bianmaqi.v".
    Found 1-bit register for signal <Q>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <DFF> synthesized.


Synthesizing Unit <bianma>.
    Related source file is "212bianmaqi.v".
    Found 1-bit xor2 for signal <Dout1>.
    Found 1-bit xor2 for signal <Dout2>.
    Found 1-bit xor4 for signal <$n0000> created at line 89.
    Summary:
	inferred   2 Xor(s).
Unit <bianma> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 6
 1-bit register                    : 6
# Xors                             : 3
 1-bit xor2                        : 2
 1-bit xor4                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : bianma.ngr
Keep Hierarchy                     : YES
Target Technology                  : acr2
Macro Preserve                     : YES
XOR Preserve                       : YES
Clock Enable                       : YES
wysiwyg                            : NO

Design Statistics
# IOs                              : 5

Cell Usage :
# FlipFlops/Latches                : 6
#      FD                          : 6
=========================================================================
CPU : 1.72 / 2.00 s | Elapsed : 1.00 / 2.00 s
 
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Total memory usage is 79976 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)