run_script.tcl

一个完整的viterbi译码程序和测试的程序

#########################################################################
#########################################################################
##
## Revision Control Information
##
## Description	:  Generic script to be customized by Megawizard 
##                 for running RTL simulation in Modelsim
##
## ALTERA Propietary
## Copyright 2003 (c) Altera Corporation
## All rights reserved
##
#########################################################################
#########################################################################

#set workdir to the path setting where design files are installed
set workdir [pwd]
set testbench_dir [file join [pwd] .. testbench]
set source_dir [file join [pwd] .. source]
#set megacore_lib_dir to the path setting where the Viterbi IP is installed
set megacore_lib_dir {c:/megacore/viterbi-v4.1.0/lib}

#set quartusdir to the path setting where Quartus II is installed
global env
if ![info exists env(QUARTUS_ROOTDIR)] {
	puts "Expected Enviroment variable QUARTUS_ROOTDIR pointing to a valid Quartus installation"
	exit
}
set quartusdir [file join $env(QUARTUS_ROOTDIR) eda sim_lib]

#set use_ipfs to indicate using the IP functional simulation models
set use_ipfs 1

#set design_name to the entity name of the Viterbi IP
set design_name "viterbi_BER"
#set viterbi_arch to the architecture values: "HYB_ATL" or "PAR_ATL"
set viterbi_arch "PAR_ATL"
#set hdl language to: "vhdl" or "verilog"
set hdl_language "vhdl"

# Set simgen model as the default simulation model
if {![info exists use_ipfs]} {
    set use_ipfs 1
}

cd $workdir
set vhd_path [file join .. sim_lib ModelSim vhdl]

#Will recompile the libraries regardless of whether the libraries exist
set bForceRecompile 1

# Close existing ModelSim simulation 
quit -sim

# Create work lib  
if {[file exist work] ==0} 	{exec vlib work}

# Create ModelSim project 
if {[file exist [project env]] > 0} {project close}
cd $workdir
if {[file exist "$workdir/viterbi_node_sync.mpf"] == 0} {
	project new $workdir viterbi_node_sync work 
} else	{
	project open viterbi_node_sync
}


if {([file exist lpm] ==0)||($bForceRecompile>0)} {
				exec vlib lpm
				exec vmap lpm lpm
				vcom -explicit -93 -work lpm "$quartusdir/220pack.vhd"
				vcom -explicit -93 -work lpm "$quartusdir/220model.vhd"
				}
exec vmap lpm lpm


if {([file exist altera_mf] ==0)||($bForceRecompile>0)} {
				exec vlib altera_mf
				exec vmap altera_mf altera_mf
				vcom -explicit -93 -work altera_mf "$quartusdir/altera_mf_components.vhd"
				vcom -explicit -93 -work altera_mf "$quartusdir/altera_mf.vhd"
				}
exec vmap altera_mf altera_mf

if {([file exist sgate] ==0) ||($bForceRecompile>0)}    {
	            			exec vlib sgate
				exec vmap sgate sgate
            				vcom -explicit -93 -work sgate "$quartusdir/sgate_pack.vhd"
            				vcom -explicit -93 -work sgate "$quartusdir/sgate.vhd"
                                     }
exec vmap sgate sgate


switch $viterbi_arch {
    HYB_ATL {set st "hyb"}
    PAR_ATL {set st "par"}
    default {error "The viterbi architecture \"$viterbi_arch\" was not recognised!"}
}


switch $hdl_language {
    vhdl    {set ext_wrapper "vhd"}
    verilog {set ext_wrapper "v"}
    default {error "Value assigned to variable hdl_language \"$hdl_language\" was not recognised!"}
}
if {[file exists "$source_dir/${design_name}.vho"]} {
	puts "Info: IPFS file ${design_name}.vho found"
	set ext_ipfs "vho"
} elseif {[file exists "$source_dir/${design_name}.vo"]} {
	puts "Info: IPFS file ${design_name}.vo found"
	set ext_ipfs "vo"
} else {
	puts "Info: No IPFS model found. Simulating with ModelSim precompiled library"
	set use_ipfs 0
}


catch {
	vdel -lib vit_work -all
}

catch {
	vlib vit_work
	vmap vit_work [file join $workdir vit_work]
	if {$use_ipfs == 1} {
		vmap viterbi [file join $workdir vit_work]
	}
	else {
		vmap viterbi [file join $megacore_lib_dir $vhd_path Viterbi]
		vcom -work viterbi -force_refresh
	}
} 


catch {
	if {$use_ipfs == 1} {
		vcom -explicit -93 -work vit_work "$testbench_dir/vi_interface.vhd"
		vcom -explicit -93 -work vit_work "$testbench_dir/vi_functions.vhd"
		vcom -explicit -93 -work vit_work "$testbench_dir/vi_bench.vhd"
		vcom -explicit -93 -work vit_work "$testbench_dir/auk_vit_vit_var_enc_ent.vhd"
		vcom -explicit -93 -work vit_work "$testbench_dir/auk_vit_vit_var_enc_arc_rtl.vhd"
		if {[string match "vho" $ext_ipfs]} {
			vcom -explicit -93 -work vit_work [file join $source_dir ${design_name}.vho]
		} elseif {[string match "vo" $ext_ipfs]} {
			vlog -L vit_work [file join $source_dir ${design_name}.vo]
		}
	} else {
		if {[string match "vhdl" $hdl_language]} {
			vcom -explicit -93 -work vit_work [file join $source_dir ${design_name}.vhd]
		} elseif {[string match "verilog" $hdl_language]} {
			vlog -L vit_work [file join $source_dir ${design_name}.v]
		}
	}
	
		
	vcom -explicit -93 -work vit_work "$source_dir/mux_2d.vhd"
	vcom -explicit -93 -work vit_work "$source_dir/ber_threshold.vhd"
	vcom -explicit -93 -work vit_work "$source_dir/rotate_node_sync.vhd"
	vcom -explicit -93 -work vit_work "$source_dir/ber_node_sync.vhd"
	vcom -explicit -93 -work vit_work "$source_dir/viterbi_node_sync.vhd"
	vcom -explicit -93 -work vit_work "$testbench_dir/Bench_vit_${st}_atl_ent_node_sync.vhd"
	vcom -explicit -93 -work vit_work "$testbench_dir/Bench_vit_${st}_atl_arc_ben_node_sync.vhd"
	vcom -explicit -93 -work vit_work "$testbench_dir/viterbi_node_sync_testbench.vhd"
}

catch {
	vsim vit_work.cfg_testbench
	source wave.do
	run -all
}