viterbi_ber_vsim_script.tcl

一个完整的viterbi译码程序和测试的程序

#########################################################################
#########################################################################
##
## Revision Control Information
##
## Description	:  Generic script to be customized by Megawizard 
##                 for running RTL simulation in Modelsim
##
## ALTERA Propietary
## Copyright 2003 (c) Altera Corporation
## All rights reserved
##
#########################################################################
#########################################################################

set megacore_wrapper_dir {C:/altera/design_examples/viterbi_node_sync/source}
set megacore_lib_dir {C:/software/altera/megacore/viterbi-v4.1.0/lib}

##from entity_name.esf
set design_name "viterbi_BER"
## for architecture values are "HYB_ATL" or "PAR_ATL"
set viterbi_arch "PAR_ATL"
set hdl_language "vhdl"

# Set simgen model as the default simulation model
if {![info exists use_ipfs]} {
    set use_ipfs 1
}


cd $megacore_wrapper_dir

set vhd_path [file join .. sim_lib ModelSim vhdl]

switch $viterbi_arch {
    HYB_ATL {set st "hyb"}
    PAR_ATL {set st "par"}
    default {error "The viterbi architecture \"$viterbi_arch\" was not recognised!"}
}

## Assuming verilog wrapper means the user will select verilog for ipfs. That may not be 
## necessarily true: do a search for file and its extension to determine that 

switch $hdl_language {
    vhdl    {set ext_wrapper "vhd"}
    verilog {set ext_wrapper "v"}
    default {error "Value assigned to variable hdl_language \"$hdl_language\" was not recognised!"}
}
if {[file exists ${design_name}.vho]} {
	puts "Info: IPFS file ${design_name}.vho found"
	set ext_ipfs "vho"
} elseif {[file exists ${design_name}.vo]} {
	puts "Info: IPFS file ${design_name}.vo found"
	set ext_ipfs "vo"
} else {
	puts "Info: No IPFS model found. Simulating with ModelSim precompiled library"
	set use_ipfs 0
}


catch {
	vdel -lib vit_work -all
}

catch {
	vlib vit_work
	vmap vit_work [file join $megacore_wrapper_dir vit_work]
	if {$use_ipfs == 1} {
		vmap viterbi [file join $megacore_wrapper_dir vit_work]
	} else {
		vmap viterbi [file join $megacore_lib_dir $vhd_path Viterbi]
		vcom -work viterbi -force_refresh
	}
} 

## Note: For verilog wrapper / ipfs model a dual license is required in modelsim
## in order to use the provided VHDL testbench

catch {
	if {$use_ipfs == 1} {
		vcom -explicit -93 -work vit_work [file join $megacore_lib_dir $vhd_path testbench vi_interface.vhd]
		vcom -explicit -93 -work vit_work [file join $megacore_lib_dir $vhd_path testbench vi_functions.vhd]
		vcom -explicit -93 -work vit_work [file join $megacore_lib_dir $vhd_path testbench vi_bench.vhd]
		vcom -explicit -93 -work vit_work [file join $megacore_lib_dir $vhd_path testbench auk_vit_vit_var_enc_ent.vhd]
		vcom -explicit -93 -work vit_work [file join $megacore_lib_dir $vhd_path testbench auk_vit_vit_var_enc_arc_rtl.vhd]
		if {[string match "vho" $ext_ipfs]} {
			vcom -explicit -93 -work vit_work [file join $megacore_wrapper_dir ${design_name}.vho]
		} elseif {[string match "vo" $ext_ipfs]} {
			vlog -L vit_work [file join $megacore_wrapper_dir ${design_name}.vo]
		}
	} else {
		if {[string match "vhdl" $hdl_language]} {
			vcom -explicit -93 -work vit_work [file join $megacore_wrapper_dir ${design_name}.vhd]
		} elseif {[string match "verilog" $hdl_language]} {
			vlog -L vit_work [file join $megacore_wrapper_dir ${design_name}.v]
		}
	}
	vcom -explicit -93 -work vit_work [file join $megacore_lib_dir $vhd_path testbench Bench_vit_${st}_atl_ent.vhd]
	vcom -explicit -93 -work vit_work [file join $megacore_lib_dir $vhd_path testbench Bench_vit_${st}_atl_arc_ben.vhd]
	vcom -explicit -93 -work vit_work [file join $megacore_wrapper_dir ${design_name}_testbench.vhd]
}

catch {
	vsim vit_work.cfg_testbench
	add wave sim:/testbench/test_controller/*
	run -all
}