viterbi_ber_vital_script.tcl

一个完整的viterbi译码程序和测试的程序

#########################################################################
#########################################################################
##
## Revision Control Information
##
## Description	:  Generic script to be customized by Megawizard 
##                 for running VITAL simulation in Modelsim
##
## ALTERA Propietary
## Copyright 2003 (c) Altera Corporation
## All rights reserved
##
#########################################################################
#########################################################################


set megacore_wrapper_dir {C:/altera/design_examples/viterbi_node_sync/source}
set megacore_lib_dir {C:/software/altera/megacore/viterbi-v4.1.0/lib}

##from entity_name.esf
set design_name "viterbi_BER"
## for architecture values are "HYB_ATL" or "PAR_ATL"
set viterbi_arch "PAR_ATL"
set hdl_language "vhdl"

set start_directory [pwd]
cd $megacore_wrapper_dir

set vhd_path [file join .. sim_lib ModelSim vhdl]

switch $viterbi_arch {
    HYB_ATL {set st "hyb"}
    PAR_ATL {set st "par"}
    default {error "The viterbi architecture \"$viterbi_arch\" was not recognised!"}
}


catch {
	vdel -lib vit_work -all
}

catch {
	vlib vit_work
	## the path below is the location of the wrapper
	vmap vit_work [file join $megacore_wrapper_dir vit_work]
	vmap viterbi [file join $megacore_lib_dir $vhd_path Viterbi]
}

catch {
## Refreshing the viterbi library
vcom -work viterbi -force_refresh
}

catch {
vcom -explicit -93 -work vit_work [file join $megacore_wrapper_dir simulation modelsim ${design_name}.vho]
vcom -explicit -93 -work vit_work [file join $megacore_lib_dir $vhd_path testbench Bench_vit_${st}_atl_ent.vhd]
vcom -explicit -93 -work vit_work [file join $megacore_lib_dir $vhd_path testbench Bench_vit_${st}_atl_arc_ben.vhd]
vcom -explicit -93 -work vit_work [file join $megacore_wrapper_dir ${design_name}_testbench.vhd]
}

catch {
vsim vit_work.cfg_testbench -sdftyp /testbench/wrapper_inst=./simulation/modelsim/${design_name}_vhd.sdo
add wave sim:/testbench/test_controller/*
force /testbench/wrapper_inst/devclrn 0
run 3 ns
force /testbench/wrapper_inst/devclrn 1
run -all
}