ber_node_sync.vhd

一个完整的viterbi译码程序和测试的程序

-------------------------------------------------------------------------
-------------------------------------------------------------------------
--
-- Revision Control Information
--
-- Description	:  
--
-- Copyright 2003 (c) Altera Corporation
-- All rights reserved
--
-------------------------------------------------------------------------
-------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

-- The following library Viterbi clause is needed because this file
-- is to be compiled in a library other than Viterbi by the tcl script
-- for ModelSim users. 
-- For Visual IP users: Either create a library Viterbi or comment out the declaration
-- I have to document for SIMGEN




ENTITY ber_node_sync IS
	GENERIC
	(
		BER_threshold_val : NATURAL := 10;
		BER_monitor_len : NATURAL := 100;
		monitor_len_max : NATURAL := 10;
		numerr_max : NATURAL := 10;
		softbits : NATURAL := 4;
		n_max : NATURAL := 2
		
	);
	PORT
	(
		clk : in std_logic;
		reset : in std_logic;
		numerr : in std_logic_vector ( numerr_max downto 1);
		source_val : in std_logic;
		source_sop : in std_logic;
		source_eop : in std_logic;
       	out_sync : out std_logic;
		rr_in : in std_logic_vector(n_max * softbits downto 1);
      	rr_rotate: out std_logic_vector(n_max * softbits downto 1);
		node_state_sync : out std_logic_vector(n_max downto 1)
	);
END ber_node_sync;


ARCHITECTURE arch_ber_node_sync OF ber_node_sync IS

	
	SIGNAL node_state_sync_sig : std_logic_vector(n_max downto 1);
	SIGNAL out_sync_sig : STD_LOGIC;
	
	
	COMPONENT ber_threshold 
	GENERIC
	(
		BER_threshold_val : NATURAL;
		BER_monitor_len : NATURAL;
		monitor_len_max : NATURAL;
		numerr_max : NATURAL
		
	);
	PORT
	(
		clk : in std_logic;
		reset : in std_logic;
		numerr : in std_logic_vector ( numerr_max downto 1);
		source_val : in std_logic;
		source_sop : in std_logic;
		source_eop : in std_logic;
       		out_sync : out std_logic 
	);
	END COMPONENT;
	
	COMPONENT rotate_node_sync 
    	GENERIC
	(
		softbits : NATURAL;
		n_max : NATURAL
	);
	PORT
	(
		clk : in std_logic;
		reset : in std_logic;
		rr_in : in std_logic_vector(n_max * softbits downto 1);
       	out_sync : in std_logic;
		rr_rotate: out std_logic_vector(n_max * softbits downto 1);
		node_state_sync : out std_logic_vector(n_max downto 1)
	);
	END COMPONENT;
	
BEGIN
		
	node_state_sync <= node_state_sync_sig;
	out_sync <= out_sync_sig;
	
	ber_threshold_inst : ber_threshold
	GENERIC MAP (
		BER_threshold_val => BER_threshold_val,
		BER_monitor_len => BER_monitor_len,
		monitor_len_max => monitor_len_max,
		numerr_max => numerr_max
	)
	PORT MAP (
		clk  =>  clk,
		reset  =>  reset,
		numerr  =>  numerr,
		source_val => source_val,
		source_sop => source_sop,
		source_eop => source_eop,
		out_sync => out_sync_sig
	);
	
	rotate_node_sync_inst : rotate_node_sync
	GENERIC MAP (
		softbits => softbits,
		n_max => n_max
	)
	PORT MAP (
		clk  =>  clk,
		reset  =>  reset,
		rr_in  =>  rr_in,
		out_sync => out_sync_sig,
		rr_rotate => rr_rotate,
		node_state_sync => node_state_sync_sig
	);
	

END arch_ber_node_sync;