viterbi_ber.cmp

一个完整的viterbi译码程序和测试的程序

-- Generated by Viterbi Compiler 4.1.0 [Altera, IP Toolbench v1.2.5 build28]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2004 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

component viterbi_BER
	PORT (
		clk	: IN STD_LOGIC;
		reset	: IN STD_LOGIC;
		sink_dav_master	: IN STD_LOGIC;
		source_ena_slave	: IN STD_LOGIC;
		sink_val	: IN STD_LOGIC;
		sink_sop	: IN STD_LOGIC;
		sink_eop	: IN STD_LOGIC;
		rr	: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
		eras_sym	: IN STD_LOGIC_VECTOR (2 DOWNTO 1);
		tr_init_state	: IN STD_LOGIC_VECTOR (6 DOWNTO 1);
		tb_type	: IN STD_LOGIC;
		tb_length	: IN STD_LOGIC_VECTOR (6 DOWNTO 1);
		sink_ena_master	: OUT STD_LOGIC;
		source_dav_slave	: OUT STD_LOGIC;
		source_val	: OUT STD_LOGIC;
		source_sop	: OUT STD_LOGIC;
		source_eop	: OUT STD_LOGIC;
		decbit	: OUT STD_LOGIC;
		normalizations	: OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
		bestadd	: OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
		bestmet	: OUT STD_LOGIC_VECTOR (9 DOWNTO 1);
		numerr	: OUT STD_LOGIC_VECTOR (14 DOWNTO 1)
	);
end component;