rotate_node_sync.vhd

一个完整的viterbi译码程序和测试的程序

-------------------------------------------------------------------------
-------------------------------------------------------------------------
--
-- Revision Control Information
--
-- Description	:  
--
-- Copyright 2003 (c) Altera Corporation
-- All rights reserved
--
-------------------------------------------------------------------------
-------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_signed.ALL;



ENTITY rotate_node_sync IS
    GENERIC
	(
		softbits : NATURAL := 4;
		n_max : NATURAL := 2
	);
	PORT
	(
		clk : in std_logic;
		reset : in std_logic;
		rr_in : in std_logic_vector(n_max * softbits downto 1);
       	out_sync : in std_logic;
		rr_rotate: out std_logic_vector(n_max * softbits downto 1);
		node_state_sync : out std_logic_vector(n_max downto 1)
	);
END rotate_node_sync;


ARCHITECTURE arch_rotate_node_sync OF rotate_node_sync IS
	
	SIGNAL R1 : STD_LOGIC_VECTOR(softbits downto 1);
	SIGNAL R2 : STD_LOGIC_VECTOR(softbits downto 1);
	SIGNAL node_state_sync_sig : STD_LOGIC_VECTOR(n_max downto 1);
	SIGNAL R1_inv : STD_LOGIC_VECTOR(softbits downto 1);
	SIGNAL R2_inv : STD_LOGIC_VECTOR(softbits downto 1);
	
	
	
    COMPONENT mux_2d 
	PORT
	(
		clock		: IN STD_LOGIC ;
		data3x		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		data2x		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		data1x		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		data0x		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		sel		: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
		result		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
	);
	END COMPONENT;
	
	
BEGIN
    
    	
	R1 <= rr_in(2*softbits downto softbits+1);
	R2 <= rr_in(softbits downto 1);
	R1_inv <= -R1;
	R2_inv <= -R2;
	node_state_sync <=	node_state_sync_sig;
	


	PROCESS (clk, reset)
	  	variable sel_sig : integer range 0 to 20;
		BEGIN
			IF reset = '1' THEN
			    sel_sig := 1;
			    node_state_sync_sig <= (others => '0');
			ELSIF rising_edge(clk) THEN
				IF (out_sync = '1') THEN
					sel_sig := sel_sig + 1;
				END IF;
				node_state_sync_sig <= CONV_STD_LOGIC_VECTOR(sel_sig, n_max);
			END IF;
		END PROCESS;
		
		mux_2d_inst1 : mux_2d PORT MAP (
		clock	 => clk,
		data3x	 => R1,
		data2x	 => R2_inv,
		data1x	 => R1_inv,
		data0x	 => R2,
		sel	 => node_state_sync_sig,
		result	 => rr_rotate(softbits downto 1)
		);
		
		mux_2d_inst2 : mux_2d PORT MAP (
		clock	 => clk,
		data3x	 => R2_inv,
		data2x   => R1_inv,
		data1x	 => R2,
		data0x	 => R1,
		sel	 => node_state_sync_sig,
		result	 => rr_rotate(2*softbits downto softbits + 1)
		);
		
	
END arch_rotate_node_sync;