viterbi_ber_logiclock_script.tcl

一个完整的viterbi译码程序和测试的程序

#########################################################################
#########################################################################
##
## Revision Control Information
##
## Description  :  This script is a template on which the Megawizard
##                 will produce a logiclock script for parallel decoder
##
## ALTERA Propietary
## Copyright 2002 (c) Altera Corporation
## All rights reserved
##
#########################################################################
#########################################################################

set megacore_wrapper_dir {C:/altera/design_examples/viterbi_node_sync/source}
set megacore_lib_dir {C:/software/altera/megacore/viterbi-v4.1.0/lib}

##from entity_name.esf
set design_name "viterbi_BER"
## for architecture values are "HYB_ATL" or "PAR_ATL"
set viterbi_arch "PAR_ATL"
set hdl_language "vhdl"
## iterations is 2 power of L-1
set iterations 64.0

########################################################################################
############################### Add User Assignments Here ##############################

source [file join $megacore_lib_dir powerkit_lib.tcl]
do extraction


###############################################
# WHAT FOLLOWS IS A GENERIC SCRIPT THAT
# SHOULD WORK FOR ALL PARALLEL VITERBI DECODER CORES
#
# LOGICLOCK_CODE_SECTION_BEGIN


set top_region_name "${viterbi_arch}_$design_name"
create_llr "$top_region_name" $design_name "AUTO" "FLOATING" ""
create_llr "BER" $design_name "AUTO" "FLOATING" "$top_region_name"
create_llr "TRB" $design_name "AUTO" "FLOATING" "$top_region_name"
create_llr "BSMP" $design_name "AUTO" "FLOATING" "$top_region_name"

logiclock $design_name add nodes BSMP "*metric_processing*" ""
logiclock $design_name add nodes "BER" "*ber_used*" ""
logiclock $design_name add nodes "TRB" "*traceback*" ""

if {[string match -nocase "PAR_ATL" $viterbi_arch]} {
	set half_states [expr "$iterations / 2"]
	for {set i 1} {$i <= $iterations} {incr i} {
		create_llr to_bms_q_$i $design_name "AUTO" "FLOATING" "BSMP"
		if { $i <= $half_states } {
			set j [expr "2 * $i"]
			set k [expr "$j - 1"]
		} else {
			set p [expr "$i - $half_states"]
			set j [expr "2 * $p"]
			set k [expr "$j - 1"]
		}

		set src_nodes "*addbot_q* *addtop_q* *acs_${j}_*selected* *acs_${k}_*selected*"
		set dst_nodes "*acs_${i}_*selected* *acs_${i}_*a_ge_b"
		logiclock $design_name expand path to_bms_q_$i $src_nodes $dst_nodes "exclude" "" "" "" "" "0" 6
	}
}

# LOGICLOCK_CODE_SECTION_END

################################## Script End ##########################################