viterbi_ber_bb.v

一个完整的viterbi译码程序和测试的程序

// Generated by Viterbi Compiler 4.1.0 [Altera, IP Toolbench v1.2.5 build28]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2004 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera.  Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
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// net list, support information, device programming or simulation file, or
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module viterbi_BER (
	clk,
	reset,
	sink_dav_master,
	source_ena_slave,
	sink_val,
	sink_sop,
	sink_eop,
	rr,
	eras_sym,
	tr_init_state,
	tb_type,
	tb_length,
	sink_ena_master,
	source_dav_slave,
	source_val,
	source_sop,
	source_eop,
	decbit,
	normalizations,
	bestadd,
	bestmet,
	numerr);

	input		clk;
	input		reset;
	input		sink_dav_master;
	input		source_ena_slave;
	input		sink_val;
	input		sink_sop;
	input		sink_eop;
	input	[8:1]	rr;
	input	[2:1]	eras_sym;
	input	[6:1]	tr_init_state;
	input		tb_type;
	input	[6:1]	tb_length;
	output		sink_ena_master;
	output		source_dav_slave;
	output		source_val;
	output		source_sop;
	output		source_eop;
	output		decbit;
	output	[8:1]	normalizations;
	output	[6:1]	bestadd;
	output	[9:1]	bestmet;
	output	[14:1]	numerr;
endmodule