bench_vit_par_atl_arc_ben_node_sync.vhd

一个完整的viterbi译码程序和测试的程序

  atl_buffer_next_state_var := atl_buffer_state;
  case atl_buffer_state is

	when out_idle =>
		if dav_source_int='1' then
			atl_buffer_next_state_var := out_dav;
		end if;
  when out_dav => 
		if dav_source_int='1' then
      atl_buffer_next_state_var := out_active;
		else
			atl_buffer_next_state_var := out_dav_s;
		end if;
	when out_hold =>
		if source_ena_slave='1' then 
			atl_buffer_next_state_var := out_active;
		end if;
	when out_active =>
		if source_ena_slave='0' and dav_source_int='1' then
      atl_buffer_next_state_var := out_hold;
    elsif source_ena_slave='1' and dav_source_int='0' then
      atl_buffer_next_state_var := out_dav_s;
		elsif source_ena_slave='0' and dav_source_int='0' then
      atl_buffer_next_state_var := out_dav_m;
    end if;
	when out_dav_m => 
		if source_ena_slave='1' then
			atl_buffer_next_state_var := out_dav_s;
		else
			atl_buffer_next_state_var := out_dav_m;
		end if;
	when out_dav_s => 
		if source_ena_slave='1' and dav_source_int='0' then
			atl_buffer_next_state_var := out_idle;
		elsif source_ena_slave='1' and dav_source_int='1' then
			atl_buffer_next_state_var := out_dav;
		--else
		elsif source_ena_slave='0' and dav_source_int='0' then
			atl_buffer_next_state_var := out_last_ena;
		elsif source_ena_slave='0' and dav_source_int='1' then
			atl_buffer_next_state_var := out_dav_m;
		end if;
	when out_last_ena => 
			atl_buffer_next_state_var := dav_toggling;
	when dav_toggling => 
		if source_ena_slave='1' and dav_source_int='0' then
			atl_buffer_next_state_var := out_idle;
		elsif source_ena_slave='1' and dav_source_int='1' then
			atl_buffer_next_state_var := out_dav;
		else
			atl_buffer_next_state_var := out_last_ena;
		end if;
	-- coverage off
	when others => atl_buffer_next_state_var := out_idle;
	-- coverage on
	end case;
	atl_buffer_next_state <= atl_buffer_next_state_var;
	
end process FSM_out;


allow_val_assert <= out_fsm_buf(1);
ena_data_sourcing <= out_fsm_buf(2) after clockOffset;
source_dav_slave <= out_fsm_buf(3);


outputs_FSM_atl: process(atl_buffer_state) 

	begin
		case atl_buffer_state is
		when out_idle =>
			out_fsm_buf <= "010";
    when out_dav =>
			out_fsm_buf <= "110";
		when out_active =>
			out_fsm_buf <= "111";
		when out_hold =>
			out_fsm_buf <= "101";
		when out_last_ena =>
			out_fsm_buf <= "100";
		when out_dav_s =>
			out_fsm_buf <= "011";
		when dav_toggling =>
			out_fsm_buf <= "001";
		when out_dav_m =>
			out_fsm_buf <= "101";
		-- coverage off
		when others => 
			out_fsm_buf <= "000";
		-- coverage on
		end case;
		
end process outputs_FSM_atl;


-- end source atlantic control.

-- latching atlantic ports for slave source to be connected to master sink
clk_atl_sink: Process (clk_int, reset_int)
	begin
		if reset_int='1' then
			source_val <= '0';
		elsif Rising_edge(clk_int) then
			source_val <= source_ena_slave and allow_val_assert after clockOffset;
		end if;
end process clk_atl_sink;



clk_atl_data_sink: Process (clk_int, reset_int)

variable bench_2_decoder_d : Std_Logic_Vector(rr_size downto 1);
variable eras_sym_d  : Std_Logic_Vector(n_max downto 1);
variable sop_source_d, eop_source_d : Std_Logic;

	begin
		if reset_int='1' then
			bench_2_decoder_shunt <= (others => '0');
			eras_sym_shunt	 <= (others => '0');
			ben_2_dec_data_pipe <= (others => (others => '0'));
			ben_2_dec_eras_pipe <= (others => (others => '0'));
			sop_source_pipe <= (others => '0');
			eop_source_pipe <= (others => '0');
			sop_source_shunt <= '0';
			eop_source_shunt <= '0';
		elsif Rising_edge(clk_int) then
			if ena_data_sourcing='1' then
				bench_2_decoder_d := ben_2_dec_data_pipe(2); 
				eras_sym_d := ben_2_dec_eras_pipe(2);
				sop_source_d := sop_source_pipe(2);
				eop_source_d := eop_source_pipe(2);
			else
				bench_2_decoder_d := bench_2_decoder_shunt; 
				eras_sym_d := eras_sym_shunt;
				sop_source_d := sop_source_shunt;
				eop_source_d := eop_source_shunt;
			end if;
			if ena_data_sourcing='1' then
				ben_2_dec_data_pipe(1) <= bench_2_decoder_s; 
				ben_2_dec_eras_pipe(1) <= eras_sym_s;
				sop_source_pipe(1) <= sop_source_gen;
				eop_source_pipe(1) <= eop_source_gen;
				ben_2_dec_data_pipe(2) <= ben_2_dec_data_pipe(1);
				ben_2_dec_eras_pipe(2) <= ben_2_dec_eras_pipe(1);
				bench_2_decoder_shunt <= ben_2_dec_data_pipe(2); 
				eras_sym_shunt <= ben_2_dec_eras_pipe(2);
				sop_source_pipe(2) <= sop_source_pipe(1);
				eop_source_pipe(2) <= eop_source_pipe(1);
				sop_source_shunt <= sop_source_pipe(2);
				eop_source_shunt <= eop_source_pipe(2);
			end if;
			if source_ena_slave='1' then
				ben_2_dec_data_pipe(3) <= bench_2_decoder_d; 
				ben_2_dec_eras_pipe(3) <= eras_sym_d;
				sop_source_pipe(3) <= sop_source_d;
				eop_source_pipe(3) <= eop_source_d;
			end if;
		end if;
end process clk_atl_data_sink;

bench_2_decoder <= ben_2_dec_data_pipe(3); 
eras_sym <= ben_2_dec_eras_pipe(3);
source_sop <= sop_source_pipe(3);
source_eop <= eop_source_pipe(3);


clk_atl_data_source: Process (clk_int, reset_int)
	begin
		if reset_int='1' then
			decbit_dec_q <= '0';
		elsif Rising_edge(clk_int) then
			if sink_val='1' then
				decbit_dec_q <= decbit_dec;
			end if;
		end if;
end process clk_atl_data_source;

clk_atl_source: Process (clk_int, reset_int)
	begin
		if reset_int='1' then
			sink_dav_master_q <= '0';
			sink_ena_master	 <= '0';
			sink_val_q <= '0';
			sink_sop_q <= '0';
			sink_eop_q <= '0';
		elsif Rising_edge(clk_int) then
			sink_dav_master_q <= sink_dav_master; -- will see
			sink_ena_master   <= sink_dav_master and allow_ena_assert after clockOffset;
			sink_val_q <= sink_val;
			sink_sop_q <= sink_sop;
			sink_eop_q <= sink_eop;
		end if;
end process clk_atl_source;


ena_source_process: process
  variable seed1, seed2: positive := 1;
	variable x: real;
begin
  if (test_for="ena_source" or test_for="both_sides") then
    allow_ena_assert <= '1';
    looping: while keep_clk_running loop
	    if sink_dav_master_q/='1' then
	    	wait until Rising_edge(sink_dav_master_q);
			end if;
	    uniform (seed1, seed2, x);
			if x < 0.2 then
			  allow_ena_assert <= '0';
				wait for clockPeriod;
				allow_ena_assert <= '1';
				wait for clockPeriod;
				allow_ena_assert <= '0';
--				wait for 2*clockPeriod;
				wait for clockPeriod;
				allow_ena_assert <= '1';
--				wait for 3*clockPeriod;
				wait for clockPeriod;
				allow_ena_assert <= '0';
				wait for clockPeriod;
				allow_ena_assert <= '1';
			elsif (0.2 <= x) and (x < 0.5) then
				allow_ena_assert <= '0';
				wait for clockPeriod;
				allow_ena_assert <= '1';
				wait for clockPeriod;
				allow_ena_assert <= '0';
				wait for 2*clockPeriod;
				allow_ena_assert <= '1';
				wait for 3*clockPeriod;
				allow_ena_assert <= '0';
				wait for clockPeriod;
				allow_ena_assert <= '1';
		  elsif (0.5 <= x) and  (x < 0.9) then
		  	allow_ena_assert <= '1';
			else
			-- long time without sinking capability
			  allow_ena_assert <= '0';
				uniform (seed1, seed2, x);
				wait for natural(10.0 * x)*clockPeriod;
				allow_ena_assert <= '1';
			end if;
		end loop looping;
	else
	  allow_ena_assert <= '1';
	end if;
	wait;
end process ena_source_process;


monitor_vit_mode: process

	FILE F: TEXT open WRITE_MODE is OUTPUT_FILE;
	FILE BER_rpt: TEXT open WRITE_MODE is "BER_rpt.txt";
	FILE N_Sync_rpt: TEXT open WRITE_MODE is "N_Sync_rpt.txt";
	variable L : Line;
	Constant single_space : STRING := " ";
	Constant strA: String(1 to 39) := "The number of errors in port numerr is ";
	Constant strB: String(1 to 30) := "The Viterbi decoder is IN sync";
	Constant strC: String(1 to 34) := "The Viterbi decoder is OUT of sync";
	Constant strD: String(1 to 52) := "Error : Unexpected state of signals insync & outsync";
	Constant strF: String(1 to 47) := "Cannot read numerr port as ber is set to unused";
	variable index : NATURAL;
	variable single_bit : CHARACTER;

begin


index := 0;

reading: while keep_clk_running loop
	
	if m_sel_fifo(m_sel_rd_cursor)=0 then
		if sink_val_q='1' then
			if decbit_dec_q='1' then
				single_bit:='1';
			elsif decbit_dec_q='0' then
				single_bit:='0';
			elsif decbit_dec_q='X' then
				single_bit:='X';
			else
				ASSERT FALSE
					REPORT "Decoded bit in Viterbi is different than 1, 0 and X" severity Warning;
			end if;
			WRITE(L, single_bit);
			WRITE(L, single_space);
			index := index+1;
			if index=20 or sink_eop_q='1' then
				WRITELINE(F, L);
				index:=0;
			end if;
		end if;
	end if;
	wait until rising_edge(clk_int);
	

end loop reading;
if m_sel_fifo(m_sel_rd_cursor)=0 then
	WRITELINE(F, L);
end if;
if test_for="BER" then
	if ber="used" then
		WRITE(L, strA);
		WRITE(L, conv_integer(arg => unsigned(numerr)) );
		WRITELINE(BER_rpt, L);
	else
		WRITE(L, strF);
		WRITELINE(BER_rpt, L);
	end if;
end if;
wait;

end process monitor_vit_mode;


------------------
-- Trellis mode logic
------------------

lfsr_clk: Process (clk_int, reset_int)
	begin
		if reset_int='1' then
			lfsr_conv_enc <= (others => '0');
		elsif Rising_edge(clk_int) then
			if sink_val='1' then
				lfsr_conv_enc(L_max) <= decbit_dec;
				if sink_sop='0' then
					lfsr_conv_enc(L_max-1 downto 1 ) <= lfsr_conv_enc(L_max downto 2);
				else
					lfsr_conv_enc(L_max-1 downto 1 ) <= (others => '0');
				end if;
			end if;
		end if;
		
end process lfsr_clk;


fg3a: For I in 1 to ncodes generate


  if_tcm1: if m_list(I)=1 generate

	 	encoding: auk_vit_vit_var_enc
	 		Generic map (n => n_list(I), L_max => L_max, L_code => L_list(I), pol_sel => I, 
	 								 ga => ga, gb => gb, gc => gc, gd => gd, ge => ge, gf => gf, gg => gg)
	 		Port map (state => lfsr_conv_enc(L_max downto 1),
	 						vector => enc_bits_rx(I)(n_list(I) downto 1) );  -- n_list will be just 2 for TCM

  end generate if_tcm1;
 	
end generate fg3a;


monitor_tcm_mode: process

	FILE F: TEXT open WRITE_MODE is OUTPUT_FILE;
	FILE FSEC: TEXT open READ_MODE is TCMSEC_FILE;
	variable L, L_sector : Line;
	variable good_read : BOOLEAN;
	Constant single_space : STRING := " ";
	variable index, sector : NATURAL;
	variable unenc_bit, enc_bit : CHARACTER;
	variable two_re_enc_bits : Std_Logic_Vector(2 downto 1);
	variable sel_code_tcm_rx : NATURAL;

begin


index := 0;
if not ENDFILE(FSEC) then
	READLINE(FSEC, L_sector);
end if;
reading: while keep_clk_running loop
	if m_sel_fifo(m_sel_rd_cursor)=1 then
		if sink_val_q='1' then
			-- read sector number
			READ(L_sector, sector, good_read);
			if decbit_dec_q='1' then
				enc_bit:='1';
			elsif decbit_dec_q='0' then
				enc_bit:='0';
			elsif decbit_dec_q='X' then
				enc_bit:='X';
			else
				ASSERT FALSE
					REPORT "Decoded bit in Viterbi is different than 1, 0 and X" severity Warning;
			end if;
			-- unencoded bit calculation
			-- sel_code has to be delayed or latched with sop_source 
			-- in order to be used consistently!
			sel_code_tcm_rx := c_sel_fifo(m_sel_rd_cursor);
			two_re_enc_bits := enc_bits_rx(sel_code_tcm_rx)(2 downto 1);
			unenc_bit := un_encoded_bit_extract(two_re_enc_bits, sector);
			WRITE(L, unenc_bit);
			WRITE(L, enc_bit);
			WRITE(L, single_space);
			index := index+1;
			if index=20 or sink_eop_q='1' then
				if not ENDFILE(FSEC) then
					READLINE(FSEC, L_sector);
				end if;
				WRITELINE(F, L);
				index:=0;
			end if;
		end if;
	end if;
	wait until rising_edge(clk_int);
	

end loop reading;


if m_sel_fifo(m_sel_rd_cursor)=1 then
	WRITELINE(F, L);
end if;
wait;

--bit= function(2 re-encoded bits, sector);
--  if 2_renc="00" then
--    if sector= 1 , 0 7 or 6 then 
--      unenc_bit:='0';
--    else
--      unenc_bit:='1';
--    end if;
--  elsif 2_renc="01" then
--    if sector= 0, 1, 2 or 7 then 
--      unenc_bit:='0';
--    else
--      unenc_bit:='1';
--    end if;
--  elsif 2_renc="10" then
--    if sector= 1, 2, 3 or 4 then 
--      unenc_bit:='0';
--    else
--      unenc_bit:='1';
--    end if;
--  elsif 2_renc="11" then
--    if sector= 0, 1, 2 or 3 then 
--      unenc_bit:='0';
--    else
--      unenc_bit:='1';
--    end if;
--  else 
--    unenc_bit :='X';
--  end if;
--

end process monitor_tcm_mode;

end architecture Bench;