vote3.vhd

用VHDL写的源代码程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--*********************************************
ENTITY vote3 IS
	PORT(men : IN std_logic_vector(2 DOWNTO 0);
		 pass,stop : BUFFER std_logic);
END vote3;
--*********************************************
ARCHITECTURE behave OF vote3 IS
BEGIN
	PROCESS(men)
		VARIABLE temp: std_logic_vector(1 DOWNTO 0);
	BEGIN
		temp:="00";
		for i in 0 to 2 loop
			if(men(i)='1') then
				temp:=temp+1;
			else
				temp:=temp+0;
			end if;
		end loop;
		pass<=temp(1);
		stop<=not(pass);
END PROCESS;
END behave;