fulladd.vhd

来自「用VHDL写的源代码程序」· VHDL 代码 · 共 33 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--*********************************************
ENTITY fulladd IS
	PORT(a,b,ci : IN std_logic;
		 sum,co : OUT std_logic);
END fulladd;
--*********************************************
ARCHITECTURE behave OF fulladd IS
BEGIN
	PROCESS(a,b,ci)
		VARIABLE temp: std_logic_vector(1 DOWNTO 0);
	BEGIN
		temp:="00";
		if a='1' then 
			temp:=temp+1; 
		end if;
		if b='1' then 
			temp:=temp+1; 
		end if;
		if ci='1' then 
			temp:=temp+1; 
		end if;
		sum<=temp(0);
		co<=temp(1);
	END PROCESS;
END behave;