alarm.vhd

以前学习VHDL语言时做的一个电子闹钟程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY alarm is 
	port(sec,min: in std_logic_vector(7 downto 0);
		 clk1,clk2: in std_logic;
         qout : out std_logic);		
END alarm;

architecture behave of alarm is 
BEGIN
	process(sec,min,clk1,clk2)
	begin
	if(sec="01010000" and min="01011001") then
		qout<=clk1;
	elsif(sec="01010010" and min="01011001") then
		qout<=clk1;
	elsif(sec="01010100" and min="01011001") then
		qout<=clk1;
	elsif(sec="01010110" and min="01011001") then
		qout<=clk1;
	elsif(sec="01011000" and min="01011001") then
		qout<=clk1;
	elsif(sec="00000000" and min="00000000") then
		qout<=clk2;
	else 
		qout<='0';
	end if;
	end process;
END behave;