select2.vhd

以前学习VHDL语言时做的一个电子闹钟程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY select2 is 
	port(clksec,clkback,a : in std_logic;
         clkout : out std_logic);		
END select2;

architecture behave of select2 is 
BEGIN
	process(clksec,clkback,a)
	begin
	if(a='0') then
		clkout<=clkback;
	elsif(a='1') then
		clkout<=clksec;
	else 
		clkout<='0';
	end if;
	end process;
END behave;