icx229al.gfl

来自「SONY公司出品的黑白CCD（44万像素）ICX229的驱动信号产生程序」· GFL 代码 · 共 3,174 行 · 第 1/5 页

top.vf
# XST (Creating Lso File) : 
top.lso
# xst flow : RunXST
top_summary.html
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
ICX229.ngc
serial.ngc
VSP2232.ngc
ICX229.ngr
serial.ngr
VSP2232.ngr
top.ngr
# Project -> New Source -> Architecture Wizard
# xst flow : RunXST
top_summary.html
ProjNav -> New -> Test Fixture
__projnav/createTF.err
# ModelSim : Simulate Behavioral Verilog Model
test3_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test3_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test3_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test3_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# xst flow : RunXST
top_summary.html
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
test2_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial_summary.html
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
serial.ngc
serial.ngr
# XST (Creating Lso File) : 
data.lso
# xst flow : RunXST
data_summary.html
# xst flow : RunXST
data.syr
data.prj
data.sprj
data.ana
data.stx
data.cmd_log
data.ngc
data.ngr
# xst flow : RunXST
top_summary.html
# Project -> New Source -> Architecture Wizard
# Project -> New Source -> Architecture Wizard
# XAW : PDCL (jhdparse)
__projnav/clk4_jhdparse_tcl.rsp
# Project -> New Source -> Architecture Wizard
# Project -> New Source -> Architecture Wizard
# XAW : PDCL (jhdparse)
__projnav/clk4_jhdparse_tcl.rsp
# Project -> New Source -> Architecture Wizard
# XAW : PDCL (jhdparse)
__projnav/clk4_jhdparse_tcl.rsp
# Project -> New Source -> Architecture Wizard
# XAW : PDCL (jhdparse)
__projnav/clk4_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# XAW : Create Schematic Symbol
clk4.spl
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
top.vf
# XAW : View HDL Source (Verilog)
clk4.v
xaw2verilog.log
# ModelSim : Simulate Behavioral Verilog Model
top_top_sch_tb.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Project -> New Source -> Architecture Wizard
# XAW : PDCL (jhdparse)
__projnav/clk4_jhdparse_tcl.rsp
# XAW : Create Schematic Symbol
clk4.spl
# Project -> New Source -> Architecture Wizard
# XAW : PDCL (jhdparse)
__projnav/clk4_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# XAW : Create Schematic Symbol
clk4.spl
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
top.vf
# XAW : View HDL Source (Verilog)
clk4.v
xaw2verilog.log
# ModelSim : Simulate Behavioral Verilog Model
top_top_sch_tb.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Project -> New Source -> Architecture Wizard
# XAW : PDCL (jhdparse)
__projnav/clk4_jhdparse_tcl.rsp
# XAW : Create Schematic Symbol
clk4.spl
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
top.vf
# XAW : View HDL Source (Verilog)
clk4.v
xaw2verilog.log
# ModelSim : Simulate Behavioral Verilog Model
top_top_sch_tb.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# xst flow : RunXST
top_summary.html
# Verilog : Create Schematic Symbol
data.spl
__projnav/jhdparse.log
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
top.vf
# XST (Creating Lso File) : 
data.lso
# xst flow : RunXST
data_summary.html
# xst flow : RunXST
data.syr
data.prj
data.sprj
data.ana
data.stx
data.cmd_log
data.ngc
data.ngr
# Schematic : View HDL Functional Model
top.vf
# Schematic : View HDL Functional Model
top.vf
# ModelSim : Simulate Behavioral Verilog Model
test3_v.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Schematic : View HDL Functional Model
top.vf
# Verilog : Create Schematic Symbol
data.spl
__projnav/jhdparse.log
# Schematic : View HDL Functional Model
top.vf
# Verilog : Create Schematic Symbol
shuju.spl
__projnav/jhdparse.log
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
top.vf
# ModelSim : Simulate Behavioral Verilog Model
top_top_sch_tb.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
top.vf
# ModelSim : Simulate Behavioral Verilog Model
top_top_sch_tb.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# xst flow : RunXST
top_summary.html
# XST (Creating Lso File) : 
top.lso
# xst flow : RunXST
top_summary.html
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
ICX229.ngc
serial.ngc
VSP2232.ngc
ICX229.ngr
serial.ngr
VSP2232.ngr
top.ngr
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
top.vf
# XST (Creating Lso File) : 
top.lso
# xst flow : RunXST
top_summary.html
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
ICX229.ngc
serial.ngc
VSP2232.ngc
ICX229.ngr
serial.ngr
VSP2232.ngr
top.ngr
# Project -> New Source -> Architecture Wizard
# XAW : PDCL (jhdparse)
__projnav/clk4_jhdparse_tcl.rsp
# XAW : Create Schematic Symbol
clk4.spl
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
top.vf
# XAW : View HDL Source (Verilog)
clk4.v
xaw2verilog.log
# XST (Creating Lso File) : 
top.lso
# xst flow : RunXST
top_summary.html
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
ICX229.ngc
serial.ngc
VSP2232.ngc
ICX229.ngr
serial.ngr
VSP2232.ngr
top.ngr
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
top.vf
# XST (Creating Lso File) : 
top.lso
# xst flow : RunXST
top_summary.html
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
ICX229.ngc
serial.ngc
VSP2232.ngc
ICX229.ngr
serial.ngr
VSP2232.ngr
top.ngr
# View RTL Schematic
top.ngr
top.ngc
# Project -> New Source -> Architecture Wizard
# XAW : PDCL (jhdparse)
__projnav/clk4_jhdparse_tcl.rsp
# XAW : Create Schematic Symbol
clk4.spl
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
top.vf
# XAW : View HDL Source (Verilog)
clk4.v
xaw2verilog.log
# XST (Creating Lso File) : 
top.lso
# xst flow : RunXST
top_summary.html
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
ICX229.ngc
serial.ngc
VSP2232.ngc
ICX229.ngr
serial.ngr
VSP2232.ngr
top.ngr
# Project -> New Source -> Architecture Wizard
# XAW : PDCL (jhdparse)
__projnav/clk4_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
top.vf
# XAW : View HDL Source (Verilog)
clk4.v
xaw2verilog.log
# XST (Creating Lso File) : 
top.lso
# xst flow : RunXST
top_summary.html
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
ICX229.ngc
serial.ngc
VSP2232.ngc
ICX229.ngr
serial.ngr
VSP2232.ngr
top.ngr
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
top.vf
# XST (Creating Lso File) : 
top.lso
# xst flow : RunXST
top_summary.html
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
ICX229.ngc
serial.ngc
VSP2232.ngc
ICX229.ngr
serial.ngr
VSP2232.ngr
top.ngr
# Project -> New Source -> Architecture Wizard
# XAW : PDCL (jhdparse)
__projnav/clk4_jhdparse_tcl.rsp
# Project -> New Source -> Architecture Wizard
# XAW : PDCL (jhdparse)
__projnav/clk4_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
top.vf
# XAW : View HDL Source (Verilog)
clk4.v
xaw2verilog.log
# XST (Creating Lso File) : 
top.lso
# xst flow : RunXST
top_summary.html
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
ICX229.ngc
serial.ngc
VSP2232.ngc
ICX229.ngr
serial.ngr
VSP2232.ngr
top.ngr
# Project -> New Source -> Architecture Wizard
# xst flow : RunXST
top_summary.html
# Project -> New Source -> Architecture Wizard
# XAW : PDCL (jhdparse)
__projnav/clk4_jhdparse_tcl.rsp
# XAW : Create Schematic Symbol
clk4.spl
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
top.vf
# XAW : View HDL Source (Verilog)
clk4.v
xaw2verilog.log
# XST (Creating Lso File) : 
top.lso
# xst flow : RunXST
top_summary.html
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
ICX229.ngc
serial.ngc
VSP2232.ngc
ICX229.ngr
serial.ngr
VSP2232.ngr
top.ngr
# Project -> New Source -> Architecture Wizard
# XAW : PDCL (jhdparse)
__projnav/clk4_jhdparse_tcl.rsp
# XAW : Create Schematic Symbol
clk4.spl
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
top.vf
# XAW : View HDL Source (Verilog)
clk4.v
xaw2verilog.log
# XST (Creating Lso File) : 
top.lso
# xst flow : RunXST
top_summary.html
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
ICX229.ngc
serial.ngc
VSP2232.ngc
ICX229.ngr
serial.ngr
VSP2232.ngr
top.ngr
# Project -> New Source -> Architecture Wizard
# XAW : PDCL (jhdparse)
__projnav/clk4_jhdparse_tcl.rsp
# Project -> New Source -> Architecture Wizard
# XAW : Create Schematic Symbol
clk4.spl
# Project -> New Source -> Architecture Wizard
# XAW : PDCL (jhdparse)
__projnav/clk4_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# XAW : Create Schematic Symbol
clk4.spl
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# xst flow : RunXST
top_summary.html
# xst flow : RunXST
top_summary.html
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
top.vf
# XAW : View HDL Source (Verilog)
clk4.v
xaw2verilog.log
# ModelSim : Simulate Behavioral Verilog Model
top_top_sch_tb.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
top.vf
# ModelSim : Simulate Behavioral Verilog Model
top_top_sch_tb.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
top.vf
# ModelSim : Simulate Behavioral Verilog Model
top_top_sch_tb.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
top_top_sch_tb.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
top_top_sch_tb.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# Project -> New Source -> Architecture Wizard
# XAW : PDCL (jhdparse)
__projnav/clk4_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
top.vf
# XAW : View HDL Source (Verilog)
clk4.v
xaw2verilog.log
# XST (Creating Lso File) : 
top.lso
# xst flow : RunXST
top_summary.html
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
ICX229.ngc
serial.ngc
VSP2232.ngc
top.ngc
ICX229.ngr
serial.ngr
VSP2232.ngr
top.ngr
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"d:\test\icx229al/_ngo"
top.ngd
top_ngdbuild.nav
top.bld
.untf
top.cmd_log
# Implementation : Map
top_summary.html
# Implementation : Map
top_map.ncd
top.ngm
top.pcf
top.nc1
top.mrp
top_map.mrp
top.mdf
top.cmd_log
MAP_NO_GUIDE_FILE_CPF "top"
top_map.ngm
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
top.twr
top.twx
top.tsi
top.cmd_log
# Implementation : Place & Route
top_summary.html
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
top.ncd
top.par
top.pad
top_pad.txt
top_pad.csv
top.pad_txt
top.dly
reportgen.log
top.xpi
top.grf
top.itr
top_last_par.ncd
top.placed_ncd_tracker
top.routed_ncd_tracker
top.cmd_log
PAR_NO_GUIDE_FILE_CPF "top"
# Implementation : Generate Post-Place & Route Simulation Model
top_timesim.v
top_timesim.nlf
top.versim_par
top.par_nlf
top.cmd_log
top_timesim.v
top_timesim.sdf
top_timesim.sdf
# ModelSim : Simulate Post-Place & Route VHDL Model
top_top_sch_tb.tdo
# ModelSim : Simulate Post-Place & Route Verilog Model
vsim.wlf
# Schematic : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
top.vf
# XST (Creating Lso File) :