cnt10.rpt

10进制计数器

Clock, Clear, Preset, Output Enable, and synchronous Load signals.


Device-Specific Information:                            d:\eda\cnt10\cnt10.rpt
cnt10

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  70    109    G     OUTPUT      t        0      0   0    0    4    0    0  COUT
   4     16    A         FF   +  t        0      0   0    2    4    5    0  CQ0 (:14)
   5     14    A         FF   +  t        0      0   0    2    3    5    0  CQ1 (:13)
   6     13    A         FF   +  t        0      0   0    2    4    4    0  CQ2 (:12)
   8     11    A         FF   +  t        1      0   0    2    4    5    0  CQ3 (:11)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                            d:\eda\cnt10\cnt10.rpt
cnt10

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

                 Logic cells placed in LAB 'A'
        +------- LC16 CQ0
        | +----- LC14 CQ1
        | | +--- LC13 CQ2
        | | | +- LC11 CQ3
        | | | | 
        | | | |   Other LABs fed by signals
        | | | |   that feed LAB 'A'
LC      | | | | | A B C D E F G H |     Logic cells that feed LAB 'A':
LC16 -> * * * * | * - - - - - * - | <-- CQ0
LC14 -> * * * * | * - - - - - * - | <-- CQ1
LC13 -> * - * * | * - - - - - * - | <-- CQ2
LC11 -> * * * * | * - - - - - * - | <-- CQ3

Pin
83   -> - - - - | - - - - - - - - | <-- CLK
73   -> * * * * | * - - - - - - - | <-- EN
74   -> * * * * | * - - - - - - - | <-- RST


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                            d:\eda\cnt10\cnt10.rpt
cnt10

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'G':

           Logic cells placed in LAB 'G'
        +- LC109 COUT
        | 
        |   Other LABs fed by signals
        |   that feed LAB 'G'
LC      | | A B C D E F G H |     Logic cells that feed LAB 'G':

Pin
83   -> - | - - - - - - - - | <-- CLK
LC16 -> * | * - - - - - * - | <-- CQ0
LC14 -> * | * - - - - - * - | <-- CQ1
LC13 -> * | * - - - - - * - | <-- CQ2
LC11 -> * | * - - - - - * - | <-- CQ3


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                            d:\eda\cnt10\cnt10.rpt
cnt10

** EQUATIONS **

CLK      : INPUT;
EN       : INPUT;
RST      : INPUT;

-- Node name is 'COUT' 
-- Equation name is 'COUT', location is LC109, type is output.
 COUT    = LCELL( _EQ001 $  VCC);
  _EQ001 =  CQ0 & !CQ1 & !CQ2 &  CQ3;

-- Node name is 'CQ0' = 'CQI0' 
-- Equation name is 'CQ0', location is LC016, type is output.
 CQ0     = DFFE( _EQ002 $  GND, GLOBAL( CLK), !RST,  VCC,  VCC);
  _EQ002 = !CQ0 & !CQ1 & !CQ2 &  CQ3 &  EN
         # !CQ0 & !CQ3 &  EN
         #  CQ0 & !EN;

-- Node name is 'CQ1' = 'CQI1' 
-- Equation name is 'CQ1', location is LC014, type is output.
 CQ1     = DFFE( _EQ003 $  GND, GLOBAL( CLK), !RST,  VCC,  VCC);
  _EQ003 = !CQ0 &  CQ1 & !CQ3 &  EN
         #  CQ0 & !CQ1 & !CQ3 &  EN
         #  CQ1 & !EN;

-- Node name is 'CQ2' = 'CQI2' 
-- Equation name is 'CQ2', location is LC013, type is output.
 CQ2     = TFFE( _EQ004, GLOBAL( CLK), !RST,  VCC,  VCC);
  _EQ004 =  CQ0 &  CQ1 & !CQ2 & !CQ3 &  EN
         #  CQ0 &  CQ1 &  CQ2 &  EN
         #  CQ2 &  CQ3 &  EN;

-- Node name is 'CQ3' = 'CQI3' 
-- Equation name is 'CQ3', location is LC011, type is output.
 CQ3     = DFFE( _EQ005 $  GND, GLOBAL( CLK), !RST,  VCC,  VCC);
  _EQ005 = !CQ0 & !CQ1 & !CQ2 &  CQ3 &  EN &  _X001
         #  CQ0 &  CQ1 &  CQ2 & !CQ3 &  EN
         #  CQ3 & !EN;
  _X001  = EXP( CQ0 &  CQ1 &  CQ2);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                     d:\eda\cnt10\cnt10.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 8,125K