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Reading component libraries for design expansion...Annotating constraints to design from file "top.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "top.ngd" ...Writing NGDBUILD log file "top.bld"...NGDBUILD done.Completed process "Translate".
Started process "Fit".Release 5.2i - CPLD Optimizer/Partitioner F.28Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Considering device XC95144XL-TQ144.Flattening design..Multi-level logic optimization...Timing optimization..........Timing driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 29 equations into 8 function blocksDesign top has been optimized and fit into device XC95144XL-10-TQ144.Completed process "Fit".
Project Navigator Auto-Make Log File-------------------------------------
JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
Scanning C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning TOP.v
Writing TOP.jhd.
JHDPARSE complete - 0 errors, 0 warnings.
Project Navigator Auto-Make Log File-------------------------------------
JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
Scanning C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning TOP.v
Writing TOP.jhd.
JHDPARSE complete - 0 errors, 0 warnings.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "top.prj"Compiling include file "TOP.v"Module <top> compiledCompiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"No errors in compilation=========================================================================* HDL Analysis *=========================================================================Analysis of file <top.prj> succeeded. Analyzing top module <top>.WARNING:Xst:905 - TOP.v line 75: The signals <EA> are missing in the sensitivity list of always block.Module <top> is correct for synthesis.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <top>. Related source file is TOP.v.WARNING:Xst:646 - Signal <iord> is assigned but never used. Found 4-bit register for signal <EA>. Found 16-bit tristate buffer for signal <DO>. Summary: inferred 16 Tristate(s).Unit <top> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 1 4-bit register : 1# Tristates : 16 1-bit tristate buffer : 16==================================================================================================================================================* Low Level Synthesis *=========================================================================Library "C:/Xilinx/xc9500xl/data/lib.xst" ConsultedLibrary "C:/Xilinx/data/librtl.xst" ConsultedOptimizing unit <top> ...Completed process "Synthesize".
Started process "Translate".Release 5.2i - ngdbuild F.28Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc top.ucf -p xc9500xl top.ngc top.ngd Reading NGO file "D:/1tank/cpld/top.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "top.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "top.ngd" ...Writing NGDBUILD log file "top.bld"...NGDBUILD done.Completed process "Translate".
Started process "Fit".Release 5.2i - CPLD Optimizer/Partitioner F.28Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Considering device XC95144XL-TQ144.Flattening design..Multi-level logic optimization...Timing optimization..........Timing driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 29 equations into 8 function blocksDesign top has been optimized and fit into device XC95144XL-10-TQ144.Completed process "Fit".Started process "Generate Timing".Release 5.2i - Timing Report Generator F.28Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Path tracing .....The number of paths traced: 140.Generating performance summary ...Generating Pad-to-Pad delay section ...Generating Clock-to-Output-Pad delay section ...Generating Setup-To-Clock-At-Pad delay section ...Generating Register-To-Register delay section ... Cycle time table for clock IOSTRB ... Cycle time table for clock RW ...top.tim has been created.Generating Stamp model files top.mod, top.data ...top.mod has been created.top.data has been created.Completed process "Generate Timing".
Started process "Generate Programming File".Release 5.2i - Programming File Generator F.28Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Completed process "Generate Programming File".
Project Navigator Auto-Make Log File-------------------------------------
JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
Scanning C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning TOP.v
Writing TOP.jhd.
JHDPARSE complete - 0 errors, 0 warnings.
Project Navigator Auto-Make Log File-------------------------------------
JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
Scanning C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning TOP.v
Writing TOP.jhd.
JHDPARSE complete - 0 errors, 0 warnings.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "top.prj"Compiling include file "TOP.v"Module <top> compiledCompiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"No errors in compilation=========================================================================* HDL Analysis *=========================================================================Analysis of file <top.prj> succeeded. Analyzing top module <top>.WARNING:Xst:905 - TOP.v line 75: The signals <EA> are missing in the sensitivity list of always block.Module <top> is correct for synthesis.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <top>. Related source file is TOP.v.WARNING:Xst:646 - Signal <iord> is assigned but never used. Found 4-bit register for signal <EA>. Found 16-bit tristate buffer for signal <DO>. Summary: inferred 16 Tristate(s).Unit <top> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 1 4-bit register : 1# Tristates : 16 1-bit tristate buffer : 16==================================================================================================================================================* Low Level Synthesis *=========================================================================Library "C:/Xilinx/xc9500xl/data/lib.xst" ConsultedLibrary "C:/Xilinx/data/librtl.xst" ConsultedOptimizing unit <top> ...Completed process "Synthesize".
Started process "Translate".Release 5.2i - ngdbuild F.28Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc top.ucf -p xc9500xl top.ngc top.ngd Reading NGO file "D:/1tank/cpld/top.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "top.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "top.ngd" ...Writing NGDBUILD log file "top.bld"...NGDBUILD done.Completed process "Translate".
Started process "Fit".Release 5.2i - CPLD Optimizer/Partitioner F.28Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Considering device XC95144XL-TQ144.Flattening design..Multi-level logic optimization...Timing optimization..........Timing driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 29 equations into 8 function blocksDesign top has been optimized and fit into device XC95144XL-10-TQ144.Completed process "Fit".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Generate Programming File".Release 5.2i - Programming File Generator F.28Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Completed process "Generate Programming File".
Project Navigator Auto-Make Log File-------------------------------------
JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
Scanning C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning TOP.v
Writing TOP.jhd.
JHDPARSE complete - 0 errors, 0 warnings.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "top.prj"Compiling include file "TOP.v"Module <top> compiledCompiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"No errors in compilation=========================================================================* HDL Analysis *=========================================================================Analysis of file <top.prj> succeeded. ⌨️ 快捷键说明
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