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Started process "Fit".Release 5.2i - CPLD Optimizer/Partitioner F.28Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Considering device XC95144XL-TQ144.Flattening design..Multi-level logic optimization...Timing optimization..........Timing driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 29 equations into 8 function blocksDesign top has been optimized and fit into device XC95144XL-10-TQ144.Completed process "Fit".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Generate Programming File".Release 5.2i - Programming File Generator F.28Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Completed process "Generate Programming File".
Project Navigator Auto-Make Log File-------------------------------------
JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
Scanning C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning TOP.v
Writing TOP.jhd.
JHDPARSE complete - 0 errors, 0 warnings.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "top.prj"Compiling include file "TOP.v"Module <top> compiledCompiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"No errors in compilation=========================================================================* HDL Analysis *=========================================================================Analysis of file <top.prj> succeeded. Analyzing top module <top>.WARNING:Xst:905 - TOP.v line 75: The signals <EA> are missing in the sensitivity list of always block.Module <top> is correct for synthesis.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <top>. Related source file is TOP.v.WARNING:Xst:646 - Signal <iord> is assigned but never used. Found 4-bit register for signal <EA>. Found 16-bit tristate buffer for signal <DO>.WARNING:Xst:647 - Input <IS> is never used. Summary: inferred 16 Tristate(s).Unit <top> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 1 4-bit register : 1# Tristates : 16 1-bit tristate buffer : 16==================================================================================================================================================* Low Level Synthesis *=========================================================================Library "C:/Xilinx/xc9500xl/data/lib.xst" ConsultedLibrary "C:/Xilinx/data/librtl.xst" ConsultedOptimizing unit <top> ...Completed process "Synthesize".
Started process "Translate".Release 5.2i - ngdbuild F.28Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc top.ucf -p xc9500xl top.ngc top.ngd Reading NGO file "D:/1tank/cpld/top.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "top.ucf" ...ERROR:NgdBuild:755 - Line 337 in 'top.ucf': Could not find net(s) 'IS' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint.ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.ERROR:NgdBuild:19 - Errors found while parsing constraint file "top.ucf".Writing NGDBUILD log file "top.bld"...Error: Completed process "Translate".
Project Navigator Auto-Make Log File-------------------------------------
JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
Scanning C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning TOP.v
Writing TOP.jhd.
JHDPARSE complete - 0 errors, 0 warnings.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "top.prj"Compiling include file "TOP.v"Module <top> compiledCompiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"No errors in compilation=========================================================================* HDL Analysis *=========================================================================Analysis of file <top.prj> succeeded. Analyzing top module <top>.WARNING:Xst:905 - TOP.v line 75: The signals <EA> are missing in the sensitivity list of always block.Module <top> is correct for synthesis.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <top>. Related source file is TOP.v.WARNING:Xst:646 - Signal <iord> is assigned but never used. Found 4-bit register for signal <EA>. Found 16-bit tristate buffer for signal <DO>. Summary: inferred 16 Tristate(s).Unit <top> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 1 4-bit register : 1# Tristates : 16 1-bit tristate buffer : 16==================================================================================================================================================* Low Level Synthesis *=========================================================================Library "C:/Xilinx/xc9500xl/data/lib.xst" ConsultedLibrary "C:/Xilinx/data/librtl.xst" ConsultedOptimizing unit <top> ...Completed process "Synthesize".
Started process "Translate".Release 5.2i - ngdbuild F.28Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc top.ucf -p xc9500xl top.ngc top.ngd Reading NGO file "D:/1tank/cpld/top.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "top.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "top.ngd" ...Writing NGDBUILD log file "top.bld"...NGDBUILD done.Completed process "Translate".
Started process "Fit".Release 5.2i - CPLD Optimizer/Partitioner F.28Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Considering device XC95144XL-TQ144.Flattening design..Multi-level logic optimization...Timing optimization..........Timing driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 29 equations into 8 function blocksDesign top has been optimized and fit into device XC95144XL-10-TQ144.Completed process "Fit".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Generate Programming File".Release 5.2i - Programming File Generator F.28Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Completed process "Generate Programming File".
Project Navigator Auto-Make Log File-------------------------------------
JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
Scanning C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning TOP.v
Writing TOP.jhd.
JHDPARSE complete - 0 errors, 0 warnings.
Project Navigator Auto-Make Log File-------------------------------------
JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
Scanning C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning TOP.v
Writing TOP.jhd.
JHDPARSE complete - 0 errors, 0 warnings.
Project Navigator Auto-Make Log File-------------------------------------
JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
Scanning C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning TOP.v
Writing TOP.jhd.
JHDPARSE complete - 0 errors, 0 warnings.
Project Navigator Auto-Make Log File-------------------------------------
JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
Scanning C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning TOP.v
Writing TOP.jhd.
JHDPARSE complete - 0 errors, 0 warnings.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "top.prj"Compiling include file "TOP.v"Module <top> compiledCompiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"No errors in compilation=========================================================================* HDL Analysis *=========================================================================Analysis of file <top.prj> succeeded. Analyzing top module <top>.WARNING:Xst:905 - TOP.v line 75: The signals <EA> are missing in the sensitivity list of always block.Module <top> is correct for synthesis.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <top>. Related source file is TOP.v.WARNING:Xst:646 - Signal <iord> is assigned but never used. Found 4-bit register for signal <EA>. Found 16-bit tristate buffer for signal <DO>. Summary: inferred 16 Tristate(s).Unit <top> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 1 4-bit register : 1# Tristates : 16 1-bit tristate buffer : 16==================================================================================================================================================* Low Level Synthesis *=========================================================================Library "C:/Xilinx/xc9500xl/data/lib.xst" ConsultedLibrary "C:/Xilinx/data/librtl.xst" ConsultedOptimizing unit <top> ...Completed process "Synthesize".
Started process "Translate".Release 5.2i - ngdbuild F.28Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc top.ucf -p xc9500xl top.ngc top.ngd Reading NGO file "D:/1tank/cpld/top.ngc" ...⌨️ 快捷键说明
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