bin27seg.vhd

使用VHDL语言

library IEEE ;
use IEEE.std_logic_1164.all;
entity bin27seg is
port(
data_in:in std_logic_vector(3 DOWNTO 0);
data_out:out std_logic_vector(6 DOWNTO 0));
end entity;
architecture bin27seg_arc of bin27seg is
begin 
     process(data_in)
   begin
      case data_in is
   when "0000"=>data_out<="1000000";
   when "0001"=>data_out<="1001111";
   when "0010"=>data_out<="0100100";
   when "0011"=>data_out<="0110000";
   when "0100"=>data_out<="0011001";
   when "0101"=>data_out<="0010010";
   when "0110"=>data_out<="0000011";
   when "0111"=>data_out<="1111000";
   when "1000"=>data_out<="0000000";
   when "1001"=>data_out<="0011000";
   when "1010"=>data_out<="0001000";
   when "1011"=>data_out<="0000011";
   when "1100"=>data_out<="0100111";
   when "1101"=>data_out<="0100001";
   when "1110"=>data_out<="0000110";
   when "1111"=>data_out<="0001110";
   when OTHERS =>NULL;
 end case;
 end process;
end architecture;