📄 sdram_control_8port.v
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// --------------------------------------------------------------------
// Copyright (c) 2007 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email: support@terasic.com
//
// --------------------------------------------------------------------
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny Chen :| 06/??/?? :| Initial Revision
// V1.1 :| Patrick Kuo :| 07/01/19 :| Change 8 Port
// --------------------------------------------------------------------
module Sdram_Control_8Port(
// HOST Side
REF_CLK,
RESET_N,
CLK,
// FIFO Write Side 1
WR1_DATA,
WR1,
WR1_ADDR,
WR1_MAX_ADDR,
WR1_LENGTH,
WR1_LOAD,
WR1_CLK,
WR1_FULL,
WR1_USE,
// FIFO Write Side 2
WR2_DATA,
WR2,
WR2_ADDR,
WR2_MAX_ADDR,
WR2_LENGTH,
WR2_LOAD,
WR2_CLK,
WR2_FULL,
WR2_USE,
// FIFO Write Side 3
WR3_DATA,
WR3,
WR3_ADDR,
WR3_MAX_ADDR,
WR3_LENGTH,
WR3_LOAD,
WR3_CLK,
WR3_FULL,
WR3_USE,
// FIFO Write Side 4
WR4_DATA,
WR4,
WR4_ADDR,
WR4_MAX_ADDR,
WR4_LENGTH,
WR4_LOAD,
WR4_CLK,
WR4_FULL,
WR4_USE,
// FIFO Read Side 1
RD1_DATA,
RD1,
RD1_ADDR,
RD1_MAX_ADDR,
RD1_LENGTH,
RD1_LOAD,
RD1_CLK,
RD1_EMPTY,
RD1_USE,
// FIFO Read Side 2
RD2_DATA,
RD2,
RD2_ADDR,
RD2_MAX_ADDR,
RD2_LENGTH,
RD2_LOAD,
RD2_CLK,
RD2_EMPTY,
RD2_USE,
// FIFO Read Side 3
RD3_DATA,
RD3,
RD3_ADDR,
RD3_MAX_ADDR,
RD3_LENGTH,
RD3_LOAD,
RD3_CLK,
RD3_EMPTY,
RD3_USE,
// FIFO Read Side 4
RD4_DATA,
RD4,
RD4_ADDR,
RD4_MAX_ADDR,
RD4_LENGTH,
RD4_LOAD,
RD4_CLK,
RD4_EMPTY,
RD4_USE,
// SDRAM Side
SA,
BA,
CS_N,
CKE,
RAS_N,
CAS_N,
WE_N,
DQ,
DQM,
SDR_CLK
);
`include "Sdram_Params.h"
/*
parameter ParWR1_ADDR = 0;
parameter ParWR1_MAX_ADDR = 640*512;
parameter ParWR2_ADDR = 22'h100000;
parameter ParWR2_MAX_ADDR = 22'h100000+320*256;
parameter ParWR3_ADDR = 22'h200000;
parameter ParWR3_MAX_ADDR = 22'h200000+640*512;
parameter ParWR4_ADDR = 22'h300000;
parameter ParWR4_MAX_ADDR = 22'h300000+320*256;
parameter ParRD1_ADDR = 640*16;
parameter ParRD1_MAX_ADDR = 640*496;
parameter ParRD2_ADDR = 22'h100000+320*8;
parameter ParRD2_MAX_ADDR = 22'h100000+320*248;
parameter ParRD3_ADDR = 22'h200000+640*16;
parameter ParRD3_MAX_ADDR = 22'h200000+640*496;
parameter ParRD4_ADDR = 22'h300000+320*8;
parameter ParRD4_MAX_ADDR = 22'h300000+320*248;
*/
// HOST Side
input REF_CLK; //System Clock
input RESET_N; //System Reset
// FIFO Write Side 1
input [`DSIZE-1:0] WR1_DATA; //Data input
input WR1; //Write Request
input [`ASIZE-1:0] WR1_ADDR; //Write start address
input [`ASIZE-1:0] WR1_MAX_ADDR; //Write max address
input [8:0] WR1_LENGTH; //Write length
input WR1_LOAD; //Write register load & fifo clear
input WR1_CLK; //Write fifo clock
output WR1_FULL; //Write fifo full
output [15:0] WR1_USE; //Write fifo usedw
// FIFO Write Side 2
input [`DSIZE-1:0] WR2_DATA; //Data input
input WR2; //Write Request
input [`ASIZE-1:0] WR2_ADDR; //Write start address
input [`ASIZE-1:0] WR2_MAX_ADDR; //Write max address
input [8:0] WR2_LENGTH; //Write length
input WR2_LOAD; //Write register load & fifo clear
input WR2_CLK; //Write fifo clock
output WR2_FULL; //Write fifo full
output [15:0] WR2_USE; //Write fifo usedw
// FIFO Write Side 3
input [`DSIZE-1:0] WR3_DATA; //Data input
input WR3; //Write Request
input [`ASIZE-1:0] WR3_ADDR; //Write start address
input [`ASIZE-1:0] WR3_MAX_ADDR; //Write max address
input [8:0] WR3_LENGTH; //Write length
input WR3_LOAD; //Write register load & fifo clear
input WR3_CLK; //Write fifo clock
output WR3_FULL; //Write fifo full
output [15:0] WR3_USE; //Write fifo usedw
// FIFO Write Side 4
input [`DSIZE-1:0] WR4_DATA; //Data input
input WR4; //Write Request
input [`ASIZE-1:0] WR4_ADDR; //Write start address
input [`ASIZE-1:0] WR4_MAX_ADDR; //Write max address
input [8:0] WR4_LENGTH; //Write length
input WR4_LOAD; //Write register load & fifo clear
input WR4_CLK; //Write fifo clock
output WR4_FULL; //Write fifo full
output [15:0] WR4_USE; //Write fifo usedw
// FIFO Read Side 1
output [`DSIZE-1:0] RD1_DATA; //Data output
input RD1; //Read Request
input [`ASIZE-1:0] RD1_ADDR; //Read start address
input [`ASIZE-1:0] RD1_MAX_ADDR; //Read max address
input [8:0] RD1_LENGTH; //Read length
input RD1_LOAD; //Read register load & fifo clear
input RD1_CLK; //Read fifo clock
output RD1_EMPTY; //Read fifo empty
output [15:0] RD1_USE; //Read fifo usedw
// FIFO Read Side 2
output [`DSIZE-1:0] RD2_DATA; //Data output
input RD2; //Read Request
input [`ASIZE-1:0] RD2_ADDR; //Read start address
input [`ASIZE-1:0] RD2_MAX_ADDR; //Read max address
input [8:0] RD2_LENGTH; //Read length
input RD2_LOAD; //Read register load & fifo clear
input RD2_CLK; //Read fifo clock
output RD2_EMPTY; //Read fifo empty
output [15:0] RD2_USE; //Read fifo usedw
// FIFO Read Side 3
output [`DSIZE-1:0] RD3_DATA; //Data output
input RD3; //Read Request
input [`ASIZE-1:0] RD3_ADDR; //Read start address
input [`ASIZE-1:0] RD3_MAX_ADDR; //Read max address
input [8:0] RD3_LENGTH; //Read length
input RD3_LOAD; //Read register load & fifo clear
input RD3_CLK; //Read fifo clock
output RD3_EMPTY; //Read fifo empty
output [15:0] RD3_USE; //Read fifo usedw
// FIFO Read Side 4
output [`DSIZE-1:0] RD4_DATA; //Data output
input RD4; //Read Request
input [`ASIZE-1:0] RD4_ADDR; //Read start address
input [`ASIZE-1:0] RD4_MAX_ADDR; //Read max address
input [8:0] RD4_LENGTH; //Read length
input RD4_LOAD; //Read register load & fifo clear
input RD4_CLK; //Read fifo clock
output RD4_EMPTY; //Read fifo empty
output [15:0] RD4_USE; //Read fifo usedw
// SDRAM Side
output [11:0] SA; //SDRAM address output
output [1:0] BA; //SDRAM bank address
output [1:0] CS_N; //SDRAM Chip Selects
output CKE; //SDRAM clock enable
output RAS_N; //SDRAM Row address Strobe
output CAS_N; //SDRAM Column address Strobe
output WE_N; //SDRAM write enable
inout [`DSIZE-1:0] DQ; //SDRAM data bus
output [`DSIZE/8-1:0] DQM; //SDRAM data mask lines
output SDR_CLK; //SDRAM clock
// Internal Registers/Wires
// Controller
reg [`ASIZE-1:0] mADDR; //Internal address
reg [8:0] mLENGTH; //Internal length
reg [`ASIZE-1:0] rWR1_ADDR; //Register write address
reg [`ASIZE-1:0] rWR1_MAX_ADDR; //Register max write address
reg [8:0] rWR1_LENGTH; //Register write length
reg [`ASIZE-1:0] rWR2_ADDR; //Register write address
reg [`ASIZE-1:0] rWR2_MAX_ADDR; //Register max write address
reg [8:0] rWR2_LENGTH; //Register write length
reg [`ASIZE-1:0] rWR3_ADDR; //Register write address
reg [`ASIZE-1:0] rWR3_MAX_ADDR; //Register max write address
reg [8:0] rWR3_LENGTH; //Register write length
reg [`ASIZE-1:0] rWR4_ADDR; //Register write address
reg [`ASIZE-1:0] rWR4_MAX_ADDR; //Register max write address
reg [8:0] rWR4_LENGTH; //Register write length
reg [`ASIZE-1:0] rRD1_ADDR; //Register read address
reg [`ASIZE-1:0] rRD1_MAX_ADDR; //Register max read address
reg [8:0] rRD1_LENGTH; //Register read length
reg [`ASIZE-1:0] rRD2_ADDR; //Register read address
reg [`ASIZE-1:0] rRD2_MAX_ADDR; //Register max read address
reg [8:0] rRD2_LENGTH; //Register read length
reg [`ASIZE-1:0] rRD3_ADDR; //Register read address
reg [`ASIZE-1:0] rRD3_MAX_ADDR; //Register max read address
reg [8:0] rRD3_LENGTH; //Register read length
reg [`ASIZE-1:0] rRD4_ADDR; //Register read address
reg [`ASIZE-1:0] rRD4_MAX_ADDR; //Register max read address
reg [8:0] rRD4_LENGTH; //Register read length
reg [3:0] WR_MASK; //Write port active mask
reg [3:0] RD_MASK; //Read port active mask
reg mWR_DONE; //Flag write done, 1 pulse SDR_CLK
reg mRD_DONE; //Flag read done, 1 pulse SDR_CLK
reg mWR,Pre_WR; //Internal WR edge capture
reg mRD,Pre_RD; //Internal RD edge capture
reg [9:0] ST; //Controller status
reg [1:0] CMD; //Controller command
reg PM_STOP; //Flag page mode stop
reg PM_DONE; //Flag page mode done
reg Read; //Flag read active
reg Write; //Flag write active
reg [`DSIZE-1:0] mDATAOUT; //Controller Data output
wire [`DSIZE-1:0] mDATAIN; //Controller Data input
wire [`DSIZE-1:0] mDATAIN1; //Controller Data input 1
wire [`DSIZE-1:0] mDATAIN2; //Controller Data input 2
wire [`DSIZE-1:0] mDATAIN3; //Controller Data input 1
wire [`DSIZE-1:0] mDATAIN4; //Controller Data input 2
wire CMDACK; //Controller command acknowledgement
// DRAM Control
reg [`DSIZE/8-1:0] DQM; //SDRAM data mask lines
reg [11:0] SA; //SDRAM address output
reg [1:0] BA; //SDRAM bank address
reg [1:0] CS_N; //SDRAM Chip Selects
reg CKE; //SDRAM clock enable
reg RAS_N; //SDRAM Row address Strobe
reg CAS_N; //SDRAM Column address Strobe
reg WE_N; //SDRAM write enable
wire [`DSIZE-1:0] DQOUT; //SDRAM data out link
wire [`DSIZE/8-1:0] IDQM; //SDRAM data mask lines
wire [11:0] ISA; //SDRAM address output
wire [1:0] IBA; //SDRAM bank address
wire [1:0] ICS_N; //SDRAM Chip Selects
wire ICKE; //SDRAM clock enable
wire IRAS_N; //SDRAM Row address Strobe
wire ICAS_N; //SDRAM Column address Strobe
wire IWE_N; //SDRAM write enable
// FIFO Control
reg OUT_VALID; //Output data request to read side fifo
reg IN_REQ; //Input data request to write side fifo
wire [15:0] write_side_fifo_rusedw1;
wire [15:0] write_side_fifo_rusedw2;
wire [15:0] write_side_fifo_rusedw3;
wire [15:0] write_side_fifo_rusedw4;
wire [15:0] read_side_fifo_wusedw1;
wire [15:0] read_side_fifo_wusedw2;
wire [15:0] read_side_fifo_wusedw3;
wire [15:0] read_side_fifo_wusedw4;
// DRAM Internal Control
wire [`ASIZE-1:0] saddr;
wire load_mode;
wire nop;
wire reada;
wire writea;
wire refresh;
wire precharge;
wire oe;
wire ref_ack;
wire ref_req;
wire init_req;
wire cm_ack;
wire active;
output CLK;
Sdram_PLL sdram_pll1 (
.inclk0(REF_CLK),
.c0(CLK),
.c1(SDR_CLK)
);
control_interface control1 (
.CLK(CLK),
.RESET_N(RESET_N),
.CMD(CMD),
.ADDR(mADDR),
.REF_ACK(ref_ack),
.CM_ACK(cm_ack),
.NOP(nop),
.READA(reada),
.WRITEA(writea),
.REFRESH(refresh),
.PRECHARGE(precharge),
.LOAD_MODE(load_mode),
.SADDR(saddr),
.REF_REQ(ref_req),
.INIT_REQ(init_req),
.CMD_ACK(CMDACK)
);
command command1(
.CLK(CLK),
.RESET_N(RESET_N),
.SADDR(saddr),
.NOP(nop),
.READA(reada),
.WRITEA(writea),
.REFRESH(refresh),
.LOAD_MODE(load_mode),
.PRECHARGE(precharge),
.REF_REQ(ref_req),
.INIT_REQ(init_req),
.REF_ACK(ref_ack),
.CM_ACK(cm_ack),
.OE(oe),
.PM_STOP(PM_STOP),
.PM_DONE(PM_DONE),
.SA(ISA),
.BA(IBA),
.CS_N(ICS_N),
.CKE(ICKE),
.RAS_N(IRAS_N),
.CAS_N(ICAS_N),
.WE_N(IWE_N)
);
sdr_data_path data_path1(
.CLK(CLK),
.RESET_N(RESET_N),
.DATAIN(mDATAIN),
.DM(2'b00),
.DQOUT(DQOUT),
.DQM(IDQM)
);
Sdram_WR_FIFO write_fifo1(
.data(WR1_DATA),
.wrreq(WR1),
.wrclk(WR1_CLK),
.aclr(WR1_LOAD),
.rdreq(IN_REQ&WR_MASK[0]),
.rdclk(CLK),
.q(mDATAIN1),
.wrfull(WR1_FULL),
.wrusedw(WR1_USE),
.rdusedw(write_side_fifo_rusedw1)
);
Sdram_WR_FIFO write_fifo2(
.data(WR2_DATA),
.wrreq(WR2),
.wrclk(WR2_CLK),
.aclr(WR2_LOAD),
.rdreq(IN_REQ&WR_MASK[1]),
.rdclk(CLK),
.q(mDATAIN2),
.wrfull(WR2_FULL),
.wrusedw(WR2_USE),
.rdusedw(write_side_fifo_rusedw2)
);
Sdram_WR_FIFO write_fifo3(
.data(WR3_DATA),
.wrreq(WR3),
.wrclk(WR3_CLK),
.aclr(WR3_LOAD),
.rdreq(IN_REQ&WR_MASK[2]),
.rdclk(CLK),
.q(mDATAIN3),
.wrfull(WR3_FULL),
.wrusedw(WR3_USE),
.rdusedw(write_side_fifo_rusedw3)
);
Sdram_WR_FIFO write_fifo4(
.data(WR4_DATA),
.wrreq(WR4),
.wrclk(WR4_CLK),
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