sdram_control_8port.v
来自「altera de2 开发板 vga lcd控制quatus 工程」· Verilog 代码 · 共 893 行 · 第 1/2 页
V
893 行
.aclr(WR4_LOAD),
.rdreq(IN_REQ&WR_MASK[3]),
.rdclk(CLK),
.q(mDATAIN4),
.wrfull(WR4_FULL),
.wrusedw(WR4_USE),
.rdusedw(write_side_fifo_rusedw4)
);
assign mDATAIN = (WR_MASK[0]) ? mDATAIN1 :
(WR_MASK[1]) ? mDATAIN2 :
(WR_MASK[2]) ? mDATAIN3 :
mDATAIN4 ;
Sdram_RD_FIFO read_fifo1(
.data(mDATAOUT),
.wrreq(OUT_VALID&RD_MASK[0]),
.wrclk(CLK),
.aclr(RD1_LOAD),
.rdreq(RD1),
.rdclk(RD1_CLK),
.q(RD1_DATA),
.wrusedw(read_side_fifo_wusedw1),
.rdempty(RD1_EMPTY),
.rdusedw(RD1_USE)
);
Sdram_RD_FIFO read_fifo2(
.data(mDATAOUT),
.wrreq(OUT_VALID&RD_MASK[1]),
.wrclk(CLK),
.aclr(RD2_LOAD),
.rdreq(RD2),
.rdclk(RD2_CLK),
.q(RD2_DATA),
.wrusedw(read_side_fifo_wusedw2),
.rdempty(RD2_EMPTY),
.rdusedw(RD2_USE)
);
Sdram_RD_FIFO read_fifo3(
.data(mDATAOUT),
.wrreq(OUT_VALID&RD_MASK[2]),
.wrclk(CLK),
.aclr(RD3_LOAD),
.rdreq(RD3),
.rdclk(RD3_CLK),
.q(RD3_DATA),
.wrusedw(read_side_fifo_wusedw3),
.rdempty(RD3_EMPTY),
.rdusedw(RD3_USE)
);
Sdram_RD_FIFO read_fifo4(
.data(mDATAOUT),
.wrreq(OUT_VALID&RD_MASK[3]),
.wrclk(CLK),
.aclr(RD4_LOAD),
.rdreq(RD4),
.rdclk(RD4_CLK),
.q(RD4_DATA),
.wrusedw(read_side_fifo_wusedw4),
.rdempty(RD4_EMPTY),
.rdusedw(RD4_USE)
);
always @(posedge CLK)
begin
SA <= (ST==SC_CL+mLENGTH) ? 12'h200 : ISA;
BA <= IBA;
CS_N <= ICS_N;
CKE <= ICKE;
RAS_N <= (ST==SC_CL+mLENGTH) ? 1'b0 : IRAS_N;
CAS_N <= (ST==SC_CL+mLENGTH) ? 1'b1 : ICAS_N;
WE_N <= (ST==SC_CL+mLENGTH) ? 1'b0 : IWE_N;
PM_STOP <= (ST==SC_CL+mLENGTH) ? 1'b1 : 1'b0;
PM_DONE <= (ST==SC_CL+SC_RCD+mLENGTH+3) ? 1'b1 : 1'b0;
DQM <= ( active && (ST>=SC_CL) ) ? ( ((ST==SC_CL+mLENGTH) && Write)? 2'b11 : 2'b00 ) : 2'b11 ;
mDATAOUT<= DQ;
end
assign DQ = oe ? DQOUT : `DSIZE'hzzzz;
assign active = Read | Write;
always@(posedge CLK or negedge RESET_N)
begin
if(RESET_N==0)
begin
CMD <= 0;
ST <= 0;
Pre_RD <= 0;
Pre_WR <= 0;
Read <= 0;
Write <= 0;
OUT_VALID <= 0;
IN_REQ <= 0;
mWR_DONE <= 0;
mRD_DONE <= 0;
end
else
begin
Pre_RD <= mRD;
Pre_WR <= mWR;
case(ST)
0: begin
if({Pre_RD,mRD}==2'b01)
begin
Read <= 1;
Write <= 0;
CMD <= 2'b01;
ST <= 1;
end
else if({Pre_WR,mWR}==2'b01)
begin
Read <= 0;
Write <= 1;
CMD <= 2'b10;
ST <= 1;
end
end
1: begin
if(CMDACK==1)
begin
CMD<=2'b00;
ST<=2;
end
end
default:
begin
if(ST!=SC_CL+SC_RCD+mLENGTH+2)
ST<=ST+1;
else
ST<=0;
end
endcase
if(Read)
begin
if(ST==SC_CL+SC_RCD+2)
OUT_VALID <= 1;
else if(ST==SC_CL+SC_RCD+mLENGTH+2)
begin
OUT_VALID <= 0;
Read <= 0;
mRD_DONE <= 1;
end
end
else
mRD_DONE <= 0;
if(Write)
begin
if(ST==SC_CL-1)
IN_REQ <= 1;
else if(ST==SC_CL+mLENGTH-1)
IN_REQ <= 0;
else if(ST==SC_CL+SC_RCD+mLENGTH)
begin
Write <= 0;
mWR_DONE<= 1;
end
end
else
mWR_DONE<= 0;
end
end
// Internal Address & Length Control
always@(posedge CLK or negedge RESET_N)
begin
if(!RESET_N)
begin
/*
rWR1_ADDR <= ParWR1_ADDR;
rWR1_MAX_ADDR <= ParWR1_MAX_ADDR;
rWR2_ADDR <= ParWR2_ADDR;
rWR2_MAX_ADDR <= ParWR2_MAX_ADDR;
rWR3_ADDR <= ParWR3_ADDR;
rWR3_MAX_ADDR <= ParWR3_MAX_ADDR;
rWR4_ADDR <= ParWR4_ADDR;
rWR4_MAX_ADDR <= ParWR4_MAX_ADDR;
rRD1_ADDR <= ParRD1_ADDR;
rRD1_MAX_ADDR <= ParRD1_MAX_ADDR;
rRD2_ADDR <= ParRD2_ADDR;
rRD2_MAX_ADDR <= ParRD2_MAX_ADDR;
rRD3_ADDR <= ParRD3_ADDR;
rRD3_MAX_ADDR <= ParRD3_MAX_ADDR;
rRD4_ADDR <= ParRD4_ADDR;
rRD4_MAX_ADDR <= ParRD4_MAX_ADDR;
*/
rWR1_ADDR <= WR1_ADDR;
rWR1_MAX_ADDR <= WR1_MAX_ADDR;
rWR2_ADDR <= WR2_ADDR;
rWR2_MAX_ADDR <= WR2_MAX_ADDR;
rWR3_ADDR <= WR3_ADDR;
rWR3_MAX_ADDR <= WR3_MAX_ADDR;
rWR4_ADDR <= WR4_ADDR;
rWR4_MAX_ADDR <= WR4_MAX_ADDR;
rRD1_ADDR <= RD1_ADDR;
rRD1_MAX_ADDR <= RD1_MAX_ADDR;
rRD2_ADDR <= RD2_ADDR;
rRD2_MAX_ADDR <= RD2_MAX_ADDR;
rRD3_ADDR <= RD3_ADDR;
rRD3_MAX_ADDR <= RD3_MAX_ADDR;
rRD4_ADDR <= RD4_ADDR;
rRD4_MAX_ADDR <= RD4_MAX_ADDR;
rWR1_LENGTH <= 256;
rWR2_LENGTH <= 256;
rWR3_LENGTH <= 256;
rWR4_LENGTH <= 256;
rRD1_LENGTH <= 256;
rRD2_LENGTH <= 256;
rRD3_LENGTH <= 256;
rRD4_LENGTH <= 256;
end
else
begin
// Write Side 1
if(WR1_LOAD)
begin
rWR1_ADDR <= WR1_ADDR;
rWR1_MAX_ADDR <= WR1_MAX_ADDR;
rWR1_LENGTH <= WR1_LENGTH;
end
else if(mWR_DONE&WR_MASK[0])
begin
if(rWR1_ADDR<rWR1_MAX_ADDR-rWR1_LENGTH)
rWR1_ADDR <= rWR1_ADDR+rWR1_LENGTH;
else
rWR1_ADDR <= WR1_ADDR;
end
// Write Side 2
if(WR2_LOAD)
begin
rWR2_ADDR <= WR2_ADDR;
rWR2_MAX_ADDR <= WR2_MAX_ADDR;
rWR2_LENGTH <= WR2_LENGTH;
end
else if(mWR_DONE&WR_MASK[1])
begin
if(rWR2_ADDR<rWR2_MAX_ADDR-rWR2_LENGTH)
rWR2_ADDR <= rWR2_ADDR+rWR2_LENGTH;
else
rWR2_ADDR <= WR2_ADDR;
end
// Write Side 3
if(WR3_LOAD)
begin
rWR3_ADDR <= WR3_ADDR;
rWR3_MAX_ADDR <= WR3_MAX_ADDR;
rWR3_LENGTH <= WR3_LENGTH;
end
else if(mWR_DONE&WR_MASK[2])
begin
if(rWR3_ADDR<rWR3_MAX_ADDR-rWR3_LENGTH)
rWR3_ADDR <= rWR3_ADDR+rWR3_LENGTH;
else
rWR3_ADDR <= WR3_ADDR;
end
// Write Side 4
if(WR4_LOAD)
begin
rWR4_ADDR <= WR4_ADDR;
rWR4_MAX_ADDR <= WR4_MAX_ADDR;
rWR4_LENGTH <= WR4_LENGTH;
end
else if(mWR_DONE&WR_MASK[3])
begin
if(rWR4_ADDR<rWR4_MAX_ADDR-rWR4_LENGTH)
rWR4_ADDR <= rWR4_ADDR+rWR4_LENGTH;
else
rWR4_ADDR <= WR4_ADDR;
end
// Read Side 1
if(RD1_LOAD)
begin
rRD1_ADDR <= RD1_ADDR;
rRD1_MAX_ADDR <= RD1_MAX_ADDR;
rRD1_LENGTH <= RD1_LENGTH;
end
else if(mRD_DONE&RD_MASK[0])
begin
if(rRD1_ADDR<rRD1_MAX_ADDR-rRD1_LENGTH)
rRD1_ADDR <= rRD1_ADDR+rRD1_LENGTH;
else
rRD1_ADDR <= RD1_ADDR;
end
// Read Side 2
if(RD2_LOAD)
begin
rRD2_ADDR <= RD2_ADDR;
rRD2_MAX_ADDR <= RD2_MAX_ADDR;
rRD2_LENGTH <= RD2_LENGTH;
end
else if(mRD_DONE&RD_MASK[1])
begin
if(rRD2_ADDR<rRD2_MAX_ADDR-rRD2_LENGTH)
rRD2_ADDR <= rRD2_ADDR+rRD2_LENGTH;
else
rRD2_ADDR <= RD2_ADDR;
end
// Read Side 3
if(RD3_LOAD)
begin
rRD3_ADDR <= RD3_ADDR;
rRD3_MAX_ADDR <= RD3_MAX_ADDR;
rRD3_LENGTH <= RD3_LENGTH;
end
else if(mRD_DONE&RD_MASK[2])
begin
if(rRD3_ADDR<rRD3_MAX_ADDR-rRD3_LENGTH)
rRD3_ADDR <= rRD3_ADDR+rRD3_LENGTH;
else
rRD3_ADDR <= RD3_ADDR;
end
// Read Side 4
if(RD4_LOAD)
begin
rRD4_ADDR <= RD4_ADDR;
rRD4_MAX_ADDR <= RD4_MAX_ADDR;
rRD4_LENGTH <= RD4_LENGTH;
end
else if(mRD_DONE&RD_MASK[3])
begin
if(rRD4_ADDR<rRD4_MAX_ADDR-rRD4_LENGTH)
rRD4_ADDR <= rRD4_ADDR+rRD4_LENGTH;
else
rRD4_ADDR <= RD4_ADDR;
end
end
end
// Auto Read/Write Control
always@(posedge CLK or negedge RESET_N)
begin
if(!RESET_N)
begin
mWR <= 0;
mRD <= 0;
mADDR <= 0;
mLENGTH <= 0;
end
else
begin
if( (mWR==0) && (mRD==0) && (ST==0) &&
(WR_MASK==0) && (RD_MASK==0) &&
(WR1_LOAD==0) && (WR2_LOAD==0) &&
(WR3_LOAD==0) && (WR4_LOAD==0) &&
(RD1_LOAD==0) && (RD2_LOAD==0) &&
(RD3_LOAD==0) && (RD4_LOAD==0))
begin
// Read Side 1
if( (read_side_fifo_wusedw1 < rRD1_LENGTH) )
begin
mADDR <= rRD1_ADDR;
mLENGTH <= rRD1_LENGTH;
WR_MASK <= 4'b0000;
RD_MASK <= 4'b0001;
mWR <= 0;
mRD <= 1;
end
// Read Side 2
else if( (read_side_fifo_wusedw2 < rRD2_LENGTH) )
begin
mADDR <= rRD2_ADDR;
mLENGTH <= rRD2_LENGTH;
WR_MASK <= 4'b0000;
RD_MASK <= 4'b0010;
mWR <= 0;
mRD <= 1;
end
// Read Side 3
else if( (read_side_fifo_wusedw3 < rRD3_LENGTH) )
begin
mADDR <= rRD3_ADDR;
mLENGTH <= rRD3_LENGTH;
WR_MASK <= 4'b0000;
RD_MASK <= 4'b0100;
mWR <= 0;
mRD <= 1;
end
// Read Side 4
else if( (read_side_fifo_wusedw4 < rRD4_LENGTH) )
begin
mADDR <= rRD4_ADDR;
mLENGTH <= rRD4_LENGTH;
WR_MASK <= 4'b0000;
RD_MASK <= 4'b1000;
mWR <= 0;
mRD <= 1;
end
// Write Side 1
else if( (write_side_fifo_rusedw1 >= rWR1_LENGTH) && (rWR1_LENGTH!=0) )
begin
mADDR <= rWR1_ADDR;
mLENGTH <= rWR1_LENGTH;
WR_MASK <= 4'b0001;
RD_MASK <= 4'b0000;
mWR <= 1;
mRD <= 0;
end
// Write Side 2
else if( (write_side_fifo_rusedw2 >= rWR2_LENGTH) && (rWR2_LENGTH!=0) )
begin
mADDR <= rWR2_ADDR;
mLENGTH <= rWR2_LENGTH;
WR_MASK <= 4'b0010;
RD_MASK <= 4'b0000;
mWR <= 1;
mRD <= 0;
end
// Write Side 3
else if( (write_side_fifo_rusedw3 >= rWR3_LENGTH) && (rWR3_LENGTH!=0) )
begin
mADDR <= rWR3_ADDR;
mLENGTH <= rWR3_LENGTH;
WR_MASK <= 4'b0100;
RD_MASK <= 4'b0000;
mWR <= 1;
mRD <= 0;
end
// Write Side 2
else if( (write_side_fifo_rusedw4 >= rWR4_LENGTH) && (rWR4_LENGTH!=0) )
begin
mADDR <= rWR4_ADDR;
mLENGTH <= rWR4_LENGTH;
WR_MASK <= 4'b1000;
RD_MASK <= 4'b0000;
mWR <= 1;
mRD <= 0;
end
end
if(mWR_DONE)
begin
WR_MASK <= 0;
mWR <= 0;
end
if(mRD_DONE)
begin
RD_MASK <= 0;
mRD <= 0;
end
end
end
endmodule
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