fifo.map.summary

来自「用VHDL语言编写的实现FIFO的设计」· SUMMARY 代码 · 共 15 行

Analysis & Synthesis Status : Successful - Fri Apr 06 11:02:46 2007
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : fifo
Top-level Entity Name : fifo
Family : Cyclone II
Total logic elements : 82
    Total combinational functions : 70
    Dedicated logic registers : 82
Total registers : 82
Total pins : 22
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0