fifo.fit.smsg

用VHDL语言编写的实现FIFO的设计

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri Apr 06 11:02:53 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off fifo -c fifo
Info: Selected device EP2C8T144C8 for design "fifo"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 174 of 174 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C5T144C8 is compatible
    Info: Device EP2C5T144I8 is compatible
    Info: Device EP2C8T144I8 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location 1
    Info: Pin ~nCSO~ is reserved at location 2
    Info: Pin ~LVDS54p/nCEO~ is reserved at location 76
Warning: No exact pin location assignment(s) for 22 pins of 22 total pins
    Info: Pin dout[0] not assigned to an exact location on the device
    Info: Pin dout[1] not assigned to an exact location on the device
    Info: Pin dout[2] not assigned to an exact location on the device
    Info: Pin dout[3] not assigned to an exact location on the device
    Info: Pin dout[4] not assigned to an exact location on the device
    Info: Pin dout[5] not assigned to an exact location on the device
    Info: Pin dout[6] not assigned to an exact location on the device
    Info: Pin dout[7] not assigned to an exact location on the device
    Info: Pin empty not assigned to an exact location on the device
    Info: Pin full not assigned to an exact location on the device
    Info: Pin wr not assigned to an exact location on the device
    Info: Pin rd not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
    Info: Pin clr not assigned to an exact location on the device
    Info: Pin din[0] not assigned to an exact location on the device
    Info: Pin din[1] not assigned to an exact location on the device
    Info: Pin din[2] not assigned to an exact location on the device
    Info: Pin din[3] not assigned to an exact location on the device
    Info: Pin din[4] not assigned to an exact location on the device
    Info: Pin din[5] not assigned to an exact location on the device
    Info: Pin din[6] not assigned to an exact location on the device
    Info: Pin din[7] not assigned to an exact location on the device
Info: Automatically promoted node clk (placed in PIN 17 (CLK0, LVDSCLK0p, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
Info: Automatically promoted node clr (placed in PIN 18 (CLK1, LVDSCLK0n, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node empty~reg0
        Info: Destination node full~reg0
        Info: Destination node data[7][0]~2313
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 20 (unused VREF, 3.30 VCCIO, 10 input, 10 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 4 total pin(s) used --  13 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  23 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  20 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 5.518 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X16_Y5; Fanout = 4; REG Node = 'y'
    Info: 2: + IC(0.563 ns) + CELL(0.624 ns) = 1.187 ns; Loc. = LAB_X17_Y5; Fanout = 6; COMB Node = 'process0~139'
    Info: 3: + IC(0.527 ns) + CELL(0.624 ns) = 2.338 ns; Loc. = LAB_X18_Y5; Fanout = 4; COMB Node = 'y~351'
    Info: 4: + IC(0.187 ns) + CELL(0.624 ns) = 3.149 ns; Loc. = LAB_X18_Y5; Fanout = 9; COMB Node = 'process0~4'
    Info: 5: + IC(0.605 ns) + CELL(0.206 ns) = 3.960 ns; Loc. = LAB_X18_Y5; Fanout = 8; COMB Node = 'dout[0]~1730'
    Info: 6: + IC(0.703 ns) + CELL(0.855 ns) = 5.518 ns; Loc. = LAB_X17_Y5; Fanout = 1; REG Node = 'dout[6]~reg0'
    Info: Total cell delay = 2.933 ns ( 53.15 % )
    Info: Total interconnect delay = 2.585 ns ( 46.85 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%
    Info: The peak interconnect region extends from location X11_Y0 to location X22_Y9
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 10 output pins without output pin load capacitance assignment
    Info: Pin "dout[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "dout[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "dout[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "dout[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "dout[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "dout[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "dout[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "dout[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "empty" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "full" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 3 warnings
    Info: Allocated 174 megabytes of memory during processing
    Info: Processing ended: Fri Apr 06 11:03:01 2007
    Info: Elapsed time: 00:00:08