addsub_c_13.v

来自「64位乘法器源码verilog,经过验证测试」· Verilog 代码 · 共 14 行

module addsub_c_13(p,y,op,s);
    input [12:0] p;
    input [8:0] y;
    input op;
    output [12:0] s;

	 wire [12:0] op_ext = {op, op, op, op, op, op, op, op, op, op, op, op, op};
	 wire [12:0] y_ext = {y[8], y[8], y[8], y[8], y[8:0]};
	 wire [12:0] y_xor = op_ext ^ y_ext;

	 assign s = p + y_xor + op;

endmodule