lastrow.v

来自「64位乘法器源码verilog,经过验证测试」· Verilog 代码 · 共 16 行

module lastrow(part,cin,s,cout);
	/* Last row of adders with full carry chain. */
    input [6:0] part;
    input [6:0] cin;
    output [6:0] s;
    output cout;
    wire [5:0] carry;
 
   assign {carry[0],s[0]} = part[0] + cin[0];
   assign {carry[1],s[1]} = part[1] + cin[1] + carry[0];
	assign {carry[2],s[2]} = part[2] + cin[2] + carry[1];
	assign {carry[3],s[3]} = part[3] + cin[3] + carry[2];
	assign {carry[4],s[4]} = part[4] + cin[4] + carry[3];
   assign {carry[5],s[5]} = part[5] + cin[5] + carry[4];
   assign {cout,s[6]} = part[6] + cin[6] + carry[5];
endmodule