addsub.v

来自「64位乘法器源码verilog,经过验证测试」· Verilog 代码 · 共 30 行

module addsub(p,y,cin,op_y,op_c,s,cout);
    input [8:0] p;
    input [8:0] y;
    input cin;
    input op_y;
    input op_c;
    output [8:0] s;
    output cout;

    reg [8:0] s_tmp;
	 reg cout_tmp;

	 always @*
	  begin
		 if (op_y==0) 
		  if (op_c==0)
		    {cout_tmp, s_tmp} = p + y + cin;
        else
			 {cout_tmp, s_tmp} = p + y - cin;
       else
		  	if (op_c==0)
		    {cout_tmp, s_tmp} = p - y + cin;
         else
			 {cout_tmp, s_tmp} = p - y - cin;
	  end

	  assign s = s_tmp;
	  assign cout = cout_tmp;
endmodule