y_mux.v

来自「64位乘法器源码verilog,经过验证测试」· Verilog 代码 · 共 19 行

module y_mux(y,sel,o);
    input [7:0] y;
    input [1:0] sel;
    output [8:0] o;

	 reg [8:0] tmp;

	 always @*
	  case (sel)
	    2'b00: tmp = 9'b000000000;
		 2'b01: tmp = {y[7], y[7:0]};
		 2'b10: tmp = y<<1;
		 2'b11: tmp = 9'b000000000;
     endcase

	  assign o = tmp;

endmodule