mult_1.v

64位乘法器源码verilog,经过验证测试

module mult_1(xi,y,p);
    input xi;
    input [7:0] y;
    output [7:0] p;

wire [7:0] xi_ext = {xi, xi, xi, xi, xi, xi, xi, xi};
assign p = xi_ext & y;

endmodule