addsub_c_9.v

64位乘法器源码verilog,经过验证测试

module addsub_c_9(p,y,op,s);
    input [8:0] p;
    input [8:0] y;
    input op;
    output [8:0] s;

	 wire [8:0] op_ext = {op, op, op, op, op, op, op, op, op};
	 wire [8:0] y_xor = y ^ op_ext;

	 assign s = p + y_xor + op;

endmodule