fulladd.v

来自「64位乘法器源码verilog,经过验证测试」· Verilog 代码 · 共 8 行

module fulladd(a,b,carryin,sum,carryout);
	input a, b, carryin; /* add these bits*/
	output sum, carryout; /* results */

	assign {carryout,sum} = a + b + carryin;
			/*  compute the sum and carry */
	endmodule