mult_s_tb.v

64位乘法器源码verilog,经过验证测试

`timescale 10ns/100ps 

module mult_s_mult_s_tb_v_tf();

// DATE:     16:12:05 04/07/2005 
// MODULE:   mult_s
// DESIGN:   mult_s
// FILENAME: mult_s_tb.v
// PROJECT:  mult
// VERSION:  


// Inputs
    reg [7:0] x;
    reg [7:0] y;


// Outputs
    wire [15:0] p;


// Bidirs


// Instantiate the UUT
    mult_s uut (
        .x(x), 
        .y(y), 
        .p(p)
        );


// Initialize Inputs
    `ifdef auto_init

        initial begin
            x = 0;
            y = 0;
        end

    `endif

initial begin
	$monitor("x = %d, y = %d, result = %d;\n",x,y,p);	
	#10 x = -8'd1; y = 2; 
	#10 x = -1; y = 2;	 
	#10 x = -8'd125; y = 3; 
	#10 x = -8'd1; y = 1; 
	#10 x = -2; y = -2; 
	#10 x = 1; y = -2; 
	#10 x = 2; y = 2; 
	#10 x = 3; y = -2; 
	#10 x = 2; y = 3; 
	#10 x = 3; y = -3; 
	#10 x = 4; y = 1; 
	#10 x = 2; y = -4; 
	#10 x = 5; y = 1; 
	#10 x = 2; y = -5; 
	#10 x = 6; y = 3; 
	#10 x = 7; y = -7; 
	#10 x = -8; y = 1; 
	#10 x = 8; y = 7; 
	#10 x = -9; y = 3; 
	#10 x = 10; y = 4; 
	#10 x = 5; y = -11; 
	#10 x = -6; y = 12; 
	#10 x = 13; y = 3; 
	#10 x = -14; y = 5; 
	#10 x = 0; y = 15; 
	#10 x = -15; y = 0; 
	#10 x = 15; y = 1; 
	#10 x = -1; y = 15; 
	#10 x = 15; y = 2; 
	#10 x = -2; y = 15; 
	#10 y = 14; x = 7;
	#10 y = 15; x = 7;
	#10 x = 15; y = 13; 
	#10 x = 13; y = 15; 
	#10 x = 15; y = 14; 
	#10 x = 14; y = 15; 
	#10 x = 15; y = 15; 
	$finish;
end

endmodule